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Joel Grodstein: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jengwei Pan, Larry L. Biro, Joel Grodstein, William J. Grundmann, Yao-Tsung Yen
    Timing Verification on a 1.2M-Device Full-Custom CMOS Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:551-554 [Conf]
  2. Joel Grodstein, Rachid Rayess, Tad Truex, Linda Shattuck, Sue Lowell, Dan Bailey, David Bertucci, Gabriel P. Bischoff, Daniel E. Dever, Mike Gowan, Roy Lane, Brian Lilly, Krishna Nagalla, Rahul Shah, Emily Shriver, Shi-Huang Yin, Shannon V. Morton
    Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:1-6 [Conf]
  3. Kundan Nepal, Hui-Yuan Song, R. Iris Bahar, Joel Grodstein
    RESTA: a robust and extendable symbolic timing analysis tool. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:407-412 [Conf]
  4. Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinatori Watanabe
    A delay model for logic synthesis of continuously-sized networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:458-462 [Conf]
  5. Joel Grodstein, Eric Lehman, Heather Harkness, Hervé J. Touati, Bill Grundmann
    Optimal latch mapping and retiming within a tree. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:242-245 [Conf]
  6. Joel Grodstein, Jim Montanaro, Susanne Marino
    Race Detection for Two-Phase Systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:20-23 [Conf]
  7. Joel Grodstein, Jengwei Pan, William J. Grundmann, Bruce Gieseke, Yao-Tsung Yen
    Constraint Identification for Timing Verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:16-19 [Conf]
  8. Joel Grodstein, Nick Rethman, Rahul Razdan, Gabriel P. Bischoff
    Automatic Detection of MOS Synchronizers for Timing Verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:304-307 [Conf]
  9. K. Kodandapani, Joel Grodstein, Antun Domic, Hervé J. Touati
    A simple algorithm for fanout optimization using high-performance buffer libraries. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:466-471 [Conf]
  10. Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness
    Logic decomposition during technology mapping. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:264-271 [Conf]
  11. Joel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard Davies
    Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:180-186 [Conf]
  12. Hui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein
    Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:70-75 [Conf]
  13. Hui-Yuan Song, R. Iris Bahar, Joel Grodstein
    Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:203-208 [Conf]
  14. R. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein
    Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:502-515 [Journal]
  15. Eric Lehman, Yosinatori Watanabe, Joel Grodstein, Heather Harkness
    Logic decomposition during technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:813-834 [Journal]
  16. Hui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein
    Timing analysis for full-custom circuits using symbolic DC formulations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1815-1830 [Journal]
  17. D. Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein
    Accurate timing analysis using SAT and pattern-dependent delay models. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1018-1023 [Conf]

  18. Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation. [Citation Graph (, )][DBLP]


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