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Publications of Author

1. Sujan Pandey, Manfred Glesner
   Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:663-668 [Conf]
   
2. Sujan Pandey, Manfred Glesner, Max Mühlhäuser
   On-Chip Communication Topology Synthesis for a Shared Memory Architecture. [Citation Graph (0, 0)][DBLP]
   FPL, 2005, pp:374-379 [Conf]
   
3. Sujan Pandey, Heiko Zimmer, Manfred Glesner, Max Mühlhäuser
   High level hardware/software communication estimation in shared memory architecture. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 2005, pp:37-40 [Conf]
   
4. Thomas Hollstein, Sujan Pandey, Manfred Glesner
   Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
   ReCoSoC, 2005, pp:85-92 [Conf]
   
5. Sujan Pandey, Manfred Glesner, Max Mühlhäuser
   Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture. [Citation Graph (0, 0)][DBLP]
   SBCCI, 2005, pp:230-235 [Conf]
   
6. Sujan Pandey, Manfred Glesner
   Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
   FPL, 2006, pp:1-6 [Conf]
   
7. Sujan Pandey, Manfred Glesner
   Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
8. Tudor Murgan, P. B. Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner
   On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2007, pp:242-254 [Conf]
   
9. Sujan Pandey, Nurten Utlu, Manfred Glesner
   Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture. [Citation Graph (0, 0)][DBLP]
   VLSI-SoC, 2006, pp:222-227 [Conf]
   
10. Tudor Murgan, O. Mitrea, Sujan Pandey, P. B. Bacinschi, Manfred Glesner
    Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:302-307 [Conf]
    
11. Sujan Pandey, Tudor Murgan, Manfred Glesner
    Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:296-301 [Conf]
    
12. Sujan Pandey, Manfred Glesner
    Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1111-1124 [Journal]
    
13. 
    Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival. [Citation Graph (, )][DBLP]
    
    
14. 
    Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs. [Citation Graph (, )][DBLP]
    
    
15. 
    Process variations aware robust on-chip bus architecture synthesis for MPSoCs. [Citation Graph (, )][DBLP]
    
    
16. 
    Co-synthesis of custom on-chip bus and memory for MPSoC architectures. [Citation Graph (, )][DBLP]