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Savithri Sundareswaran: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
    A stochastic approach To power grid analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:171-176 [Conf]
  2. Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
    Optimal placement of power supply pads and pins. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:165-170 [Conf]
  3. Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu
    A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:217-222 [Conf]
  4. David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda
    Slope Propagation in Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:338-343 [Conf]
  5. Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
    Vectorless Analysis of Supply Noise Induced Delay Variation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:184-192 [Conf]
  6. Rajendran Panda, Savithri Sundareswaran, David Blaauw
    On the interaction of power distribution network with substrate. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:388-393 [Conf]
  7. Rajeshwary Tayade, Savithri Sundereswaran, Jacob Abraham
    Small-Delay Defect Detection in the Presence of Process Variations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:711-716 [Conf]
  8. Savithri Sundareswaran, R. Venkatesan, S. Bhaskar
    An Assertion Based Technique for Transistor Level Dynamic Power Estimation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:34-37 [Conf]
  9. Savithri Sundareswaran, David Blaauw, Abhijit Dharchoudhury
    A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:175-180 [Conf]
  10. Rajendran Panda, Savithri Sundareswaran, David Blaauw
    Impact of Low-Impedance Substrate on Power Supply Integrity. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:3, pp:16-22 [Journal]
  11. David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran
    Slope propagation in static timing analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1180-1195 [Journal]
  12. Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
    Optimal placement of power-supply pads and pins. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:1, pp:144-154 [Journal]
  13. Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan
    On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:162-167 [Conf]

  14. Transistor-Specific Delay Modeling for SSTA. [Citation Graph (, )][DBLP]


  15. A novel technique for incremental analysis of on-chip power distribution networks. [Citation Graph (, )][DBLP]


  16. Total sensitivity based dfm optimization of standard library cells. [Citation Graph (, )][DBLP]


  17. Characterization of Standard Cells for Intra-Cell Mismatch Variations. [Citation Graph (, )][DBLP]


  18. Characterization of sequential cells for constraint sensitivities. [Citation Graph (, )][DBLP]


  19. A timing methodology considering within-die clock skew variations. [Citation Graph (, )][DBLP]


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