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Pankaj Pant: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pankaj Pant, Vivek De, Abhijit Chatterjee
    Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:403-408 [Conf]
  2. Pankaj Pant, Abhijit Chatterjee
    Efficient diagnosis of path delay faults in digital logic circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:471-476 [Conf]
  3. Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari
    An architectural solution for the inductive noise problem due to clock-gating. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:255-257 [Conf]
  4. Pankaj Pant, Abhijit Chatterjee
    Path-delay fault diagnosis in non-scan sequential circuits with at-speed test application. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:245-252 [Conf]
  5. Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari
    Inductive Noise Reduction at the Architectural Level. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:162-167 [Conf]
  6. Abhijit Chatterjee, Rathish Jayabharathi, Pankaj Pant, Jacob A. Abraham
    Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:354-361 [Conf]
  7. Pankaj Pant, Yuan-Chieh Hsu, Sandeep K. Gupta, Abhijit Chatterjee
    Path delay fault diagnosis in combinational circuits with implicitfault enumeration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1226-1235 [Journal]
  8. Mondira Deb Pant, Pankaj Pant, D. Scott Wills
    On-chip decoupling capacitor optimization using architectural level prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:319-326 [Journal]

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