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Publications of Author

1. Stephen Pateras, Janusz Rajski
   Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits. [Citation Graph (0, 0)][DBLP]
   DAC, 1991, pp:347-352 [Conf]
   
2. Stephen Pateras
   Embedded Diagnosis IP. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:242-243 [Conf]
   
3. Martin Bell, Givargis Danialy, Michael C. Howells, Stephen Pateras
   Bridging the gap between embedded test and ATE. [Citation Graph (0, 0)][DBLP]
   ITC, 2000, pp:55-63 [Conf]
   
4. Benoit Nadeau-Dostie, Jean-Francois Cote, Harry Hulvershorn, Stephen Pateras
   An embedded technique for at-speed interconnect testing. [Citation Graph (0, 0)][DBLP]
   ITC, 1999, pp:431-438 [Conf]
   
5. Stephen Pateras
   Security vs. Test Quality: Fully Embedded Test Approaches Are the Key to Having Both. [Citation Graph (0, 0)][DBLP]
   ITC, 2004, pp:1413- [Conf]
   
6. Stephen Pateras, Janusz Rajski
   Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits. [Citation Graph (0, 0)][DBLP]
   ITC, 1991, pp:473-482 [Conf]
   
7. Stephen Pateras, Martin S. Schmookler
   Avoiding Unknown States When Scanning Mutually Exclusive Latches. [Citation Graph (0, 0)][DBLP]
   ITC, 1995, pp:311-318 [Conf]
   
8. Stephen Pateras
   IP for Embedded Diagnosis. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2002, v:19, n:3, pp:46-55 [Journal]
   
9. Stephen Pateras
   Achieving At-Speed Structural Test. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2003, v:20, n:5, pp:26-33 [Journal]