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Publications of Author

1. Javier Resano, Daniel Mozos
   Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:119-124 [Conf]
   
2. Javier Resano, Daniel Mozos, Francky Catthoor
   A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:106-111 [Conf]
   
3. Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor
   Run-Time Scheduling for Multimedia Applications on Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
   ESTImedia, 2003, pp:156-162 [Conf]
   
4. Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor
   Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms. [Citation Graph (0, 0)][DBLP]
   FCCM, 2003, pp:278-279 [Conf]
   
5. Javier Resano
   A Specific Scheduling Flow for Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:1178-1179 [Conf]
   
6. Javier Resano, Daniel Mozos, Diederik Verkest, Serge Vernalde, Francky Catthoor
   Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
   FPL, 2003, pp:585-594 [Conf]
   
7. E. Perez Ramo, Javier Resano, Daniel Mozos, Francky Catthoor
   A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2006, pp:- [Conf]
   
8. Javier Resano, Daniel Mozos, Elena Pérez-Miñana, Hortensia Mecha, Julio Septién
   A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements. [Citation Graph (0, 0)][DBLP]
   PATMOS, 2003, pp:580-589 [Conf]
   
9. Javier Resano, Daniel Mozos, Diederik Verkest, Francky Catthoor
   A Reconfiguration Manager for Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2005, v:22, n:5, pp:452-460 [Journal]
   
10. Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor
    A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2004, v:28, n:5-6, pp:291-301 [Journal]
    
11. E. Perez Ramo, Javier Resano
    A Dual Cache for Performance and Energy Aware Reconfigurable HW. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-2 [Conf]
    
12. Javier Resano, Daniel Mozos, Francky Catthoor
    A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
    
13. Javier Resano, M. Elena Pérez, Daniel Mozos, Hortensia Mecha, Julio Septién
    Analyzing communication overheads during hardware/software partitioning. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:11, pp:1001-1007 [Journal]
    
14. 
    HW implementation of an execution manager for reconfigurable systems. [Citation Graph (, )][DBLP]
    
    
15. 
    Reducing the reconfiguration overhead: a survey of techniques. [Citation Graph (, )][DBLP]
    
    
16. 
    FPGA support for satellite computations of hyper spectral images. [Citation Graph (, )][DBLP]
    
    
17. 
    A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems. [Citation Graph (, )][DBLP]