Search the dblp DataBase

Publications of Author

1. Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi
   Systematic software-based self-test for pipelined processors. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:393-398 [Conf]
   
2. Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian
   Effective Low Power BIST for Datapaths. [Citation Graph (0, 0)][DBLP]
   DATE, 2000, pp:757- [Conf]
   
3. Antonis M. Paschalis, Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Yervant Zorian
   Deterministic software-based self-testing of embedded processor cores. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:92-96 [Conf]
   
4. Antonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian
   An Effective BIST Architecture for Fast Multiplier Cores. [Citation Graph (0, 0)][DBLP]
   DATE, 1999, pp:117-121 [Conf]
   
5. Miltiadis Hatzimihail, Mihalis Psarakis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis
   Software-Based Self-Test for Pipelined Processors: A Case Study. [Citation Graph (0, 0)][DBLP]
   DFT, 2005, pp:535-543 [Conf]
   
6. George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis
   Test Generation Methodology for High-Speed Floating Point Adders. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2005, pp:227-232 [Conf]
   
7. P. Kenterlis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis
   A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2006, pp:235-241 [Conf]
   
8. Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
   An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths. [Citation Graph (0, 0)][DBLP]
   ISQED, 2001, pp:343-349 [Conf]
   
9. Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian, Mihalis Psarakis
   An Effective BIST Scheme for Arithmetic Logic Units. [Citation Graph (0, 0)][DBLP]
   ITC, 1997, pp:868-877 [Conf]
   
10. Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian
    Low Power/Energy BIST Scheme for Datapaths. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:23-28 [Conf]
    
11. Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis
    Robust Sequential Fault Testing of Iterative Logic Arrays. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:238-244 [Conf]
    
12. Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
    Robustly Testable Array Multipliers under Realistic Sequential Cell Fault Model. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:152-157 [Conf]
    
13. Mihalis Psarakis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian
    An Effective BIST Architecture for Sequential Fault Testing in Array Multipliers. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:252-259 [Conf]
    
14. Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian
    Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:15-21 [Conf]
    
15. Nektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Mihalis Psarakis, Yervant Zorian
    Power-/Energy Efficient BIST Schemes for Processor Data Paths. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:15-28 [Journal]
    
16. Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian
    Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:10, pp:1083-1099 [Journal]
    
17. George Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis
    Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:11, pp:1449-1457 [Journal]
    
18. Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis
    Built-in sequential fault self-testing of array multipliers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:449-460 [Journal]
    
19. A. Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis
    A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:271-276 [Conf]
    
20. A. Apostolakis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis
    Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:971-975 [Journal]
    
21. 
    Functional Self-Testing for Bus-Based Symmetric Multiprocessors. [Citation Graph (, )][DBLP]
    
    
22. 
    On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors. [Citation Graph (, )][DBLP]
    
    
23. 
    Enhanced self-configurability and yield in multicore grids. [Citation Graph (, )][DBLP]
    
    
24. 
    Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors. [Citation Graph (, )][DBLP]
    
    
25. 
    Test Program Generation for Communication Peripherals in Processor-Based SoC Devices. [Citation Graph (, )][DBLP]