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Lluis Ribas: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Lluis Ribas, Jordi Carrabina
    Analysis of Switch-Level Faults by Symbolic Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:352-357 [Conf]
  2. Lluis Ribas, Jordi Carrabina
    On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:624-0 [Conf]
  3. Lluis Ribas, Jordi Carrabina
    Digital MOS Circuit Partitioning with Symbolic Modeling. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:503-508 [Conf]
  4. A. Josep Velasco, Lluis Ribas, Elena Valderrama, R. Gracia
    A Fuzzy Rule Interpreter to Build Expert Systems Based on Fuzzy Logic. An Application in Company Diagnosis. [Citation Graph (0, 0)][DBLP]
    Fuzzy Days, 1994, pp:433-438 [Conf]
  5. R. Peset Llopis, Lluis Ribas, Jordi Carrabina
    Short Destabilizing Paths in Timing Verification. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:160-163 [Conf]
  6. Lluis Ribas, Jordi Carrabina
    Symbolic Analysis for Fault Detection in Switch-Level Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1235-1238 [Conf]
  7. Jordi Riera, Lluis Ribas, A. Josep Velasco, Jordi Carrabina
    Deriving cost functions from cell libraries and real ICs to allow real area-power-delay trade-off in early stages of logic synthesis. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 1997, v:43, n:1-5, pp:119-122 [Journal]

  8. Hardware Synthesis of Parallel Machines from SystemC. [Citation Graph (, )][DBLP]

  9. On Hardware Description in ECL. [Citation Graph (, )][DBLP]

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