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Publications of Author

1. Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni
   Pushing ASIC performance in a power envelope. [Citation Graph (0, 0)][DBLP]
   DAC, 2003, pp:788-793 [Conf]
   
2. Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director
   Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:535-540 [Conf]
   
3. Ashish Srivastava, Dennis Sylvester, David Blaauw
   Statistical optimization of leakage power considering process variations using dual-Vth and sizing. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:773-778 [Conf]
   
4. Ashish Srivastava, Dennis Sylvester, David Blaauw
   Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:783-787 [Conf]
   
5. Ashish Srivastava, Dennis Sylvester, David Blaauw
   Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:718-719 [Conf]
   
6. Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David Blaauw, Dennis Sylvester
   Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:1023-1028 [Conf]
   
7. Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David Blaauw, Vladimir Zolotov
   Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:705-712 [Conf]
   
8. Ashish Srivastava, Dennis Sylvester
   A general framework for probabilistic low-power design space exploration considering process variation. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2004, pp:808-813 [Conf]
   
9. Sarvesh H. Kulkarni, Ashish Srivastava, Dennis Sylvester
   A new algorithm for improved VDD assignment in low power dual VDD systems. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2004, pp:200-205 [Conf]
   
10. Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester
    Statistical estimation of leakage current considering inter- and intra-die process variation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:84-89 [Conf]
    
11. Ashish Srivastava, Robert Bai, David Blaauw, Dennis Sylvester
    Modeling and analysis of leakage power considering within-die process variations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:64-67 [Conf]
    
12. Robert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David Blaauw
    An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:149-154 [Conf]
    
13. Ashish Srivastava, Dennis Sylvester
    Minimizing total power by simultaneous V/sub dd//V/sub th/ assignment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:665-677 [Journal]
    
14. Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester
    Statistical analysis of subthreshold leakage current for VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:2, pp:131-139 [Journal]