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Publications of Author

1. Rajesh Raina, Robert Bailey, Charles Njinda, Robert F. Molyneaux, Charlie Beh
   Efficient Testing of Clock Regenerator Circuits in Scan Designs. [Citation Graph (0, 0)][DBLP]
   DAC, 1997, pp:95-100 [Conf]
   
2. Rajesh Raina, Robert F. Molyneaux
   Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches. [Citation Graph (0, 0)][DBLP]
   Great Lakes Symposium on VLSI, 1998, pp:222-229 [Conf]
   
3. Robert F. Molyneaux
   Debug and Diagnosis in the Age of System-on-a-Chip. [Citation Graph (0, 0)][DBLP]
   ITC, 2003, pp:1303- [Conf]
   
4. Carol Pyron, Mike Alexander, James Golab, George Joos, Bruce Long, Robert F. Molyneaux, Rajesh Raina, Nandu Tendolkar
   DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor. [Citation Graph (0, 0)][DBLP]
   ITC, 1999, pp:137-146 [Conf]
   
5. Rajesh Raina, Robert Bailey, Dawit Belete, Vikram Khosa, Robert F. Molyneaux, Javier Prado, Ashutosh Razdan
   DFT advances in Motorola's Next-Generation 74xx PowerPC^TM microprocessor. [Citation Graph (0, 0)][DBLP]
   ITC, 2000, pp:131-140 [Conf]
   
6. Rajesh Raina, Charles Njinda, Robert F. Molyneaux
   How Seriously Do You Take Your Possible-Detect Faults? [Citation Graph (0, 0)][DBLP]
   ITC, 1997, pp:819-828 [Conf]
   
7. Nandu Tendolkar, Robert F. Molyneaux, Carol Pyron, Rajesh Raina
   At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor. [Citation Graph (0, 0)][DBLP]
   VTS, 2000, pp:3-8 [Conf]
   
8. Robert F. Molyneaux, Alexander Albicki
   Comments on "Ternary Scan Design for VLSI Testability". [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1989, v:38, n:2, pp:256-263 [Journal]