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Anand Rajaram: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Anand Rajaram, Jiang Hu, Rabi N. Mahapatra
    Reducing clock skew variability via cross links. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:18-23 [Conf]
  2. Anand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu
    Analytical Bound for Unwanted Clock Skew due to Wire Width Variation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:401-407 [Conf]
  3. Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert
    Practical techniques to reduce skew and its variations in buffered clock networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:592-596 [Conf]
  4. Anand Rajaram, David Z. Pan
    Variation tolerant buffered clock network synthesis with cross links. [Citation Graph (0, 0)][DBLP]
    ISPD, 2006, pp:157-164 [Conf]
  5. Anand Rajaram, David Z. Pan, Jiang Hu
    Improved algorithms for link-based non-tree clock networks for skew variability reduction. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:55-62 [Conf]
  6. Anand Rajaram, David Z. Pan
    Fast Incremental Link Insertion in Clock Networks for Skew Variability Reduction. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:79-84 [Conf]
  7. Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Chen, David Z. Pan
    Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:398-403 [Conf]
  8. Anand Rajaram, Jiang Hu, Rabi N. Mahapatra
    Reducing clock skew variability via crosslinks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1176-1182 [Journal]
  9. Anand Rajaram, Bing Lu, Jiang Hu, Rabi N. Mahapatra, Wei Guo
    Analytical bound for unwanted clock skew due to wire width variation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1869-1876 [Journal]

  10. MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks. [Citation Graph (, )][DBLP]


  11. Robust chip-level clock tree synthesis for SOC designs. [Citation Graph (, )][DBLP]


  12. Analysis and optimization of NBTI induced clock skew in gated clock trees. [Citation Graph (, )][DBLP]


  13. Practical Clock Tree Robustness Signoff Metrics. [Citation Graph (, )][DBLP]


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