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## Search the dblp DataBase
Naresh R. Shanbhag:
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## Publications of Author- Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
**Analytical Estimation of Transition Activity From Word-Level Signal Statistics.**[Citation Graph (0, 0)][DBLP] DAC, 1997, pp:582-587 [Conf] - Naresh R. Shanbhag
**Reliable and energy-efficient digital signal processing.**[Citation Graph (0, 0)][DBLP] DAC, 2002, pp:830-835 [Conf] - Naresh R. Shanbhag
**A communication-theoretic design paradigm for reliable SOCs.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:76- [Conf] - Srinivasa R. Sridhara, Naresh R. Shanbhag
**Coding for system-on-chip networks: a unified framework.**[Citation Graph (0, 0)][DBLP] DAC, 2004, pp:103-106 [Conf] - Rajamohana Hegde, Naresh R. Shanbhag
**Energy-efficiency in presence of deep submicron noise.**[Citation Graph (0, 0)][DBLP] ICCAD, 1998, pp:228-234 [Conf] - Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. (Dave) Liu, Sung-Mo Kang
**Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design.**[Citation Graph (0, 0)][DBLP] ICCAD, 2000, pp:318-321 [Conf] - Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
**Achievable bounds on signal transition activity.**[Citation Graph (0, 0)][DBLP] ICCAD, 1997, pp:126-129 [Conf] - Ming Zhang, Naresh R. Shanbhag
**A soft error rate analysis (SERA) methodology.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:111-118 [Conf] - Ganesh Balamurugan, Naresh R. Shanbhag
**Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links.**[Citation Graph (0, 0)][DBLP] ICCD, 2003, pp:254-260 [Conf] - Srinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag
**Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses.**[Citation Graph (0, 0)][DBLP] ICCD, 2004, pp:12-17 [Conf] - Hyeon-Min Bae, Naresh R. Shanbhag
**High bandwidth transimpedance amplifier design using active transmission lines.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 2003, pp:253-256 [Conf] - Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer
**Switching methods for linear turbo equalization.**[Citation Graph (0, 0)][DBLP] ISCAS (3), 2004, pp:601-604 [Conf] - Mohammad M. Mansour, Naresh R. Shanbhag
**Architecture-aware low-density parity-check codes.**[Citation Graph (0, 0)][DBLP] ISCAS (2), 2003, pp:57-60 [Conf] - Naresh R. Shanbhag, Gi-Hong Im
**Pipelined Adaptive IIR Filter Architecture.**[Citation Graph (0, 0)][DBLP] ISCAS, 1995, pp:558-561 [Conf] - Naresh R. Shanbhag, Keshab K. Parhi
**Roundoff error analysis of the pipelined ADPCM coder.**[Citation Graph (0, 0)][DBLP] ISCAS, 1993, pp:886-889 [Conf] - Naresh R. Shanbhag, Keshab K. Parhi
**A Pipelined Adaptive Differential Vector Quantizer for Low-power Speech Coding Applications.**[Citation Graph (0, 0)][DBLP] ISCAS, 1993, pp:1956-1958 [Conf] - Byonghyo Shim, Naresh R. Shanbhag
**Performance analysis of algorithmic noise-tolerance techniques.**[Citation Graph (0, 0)][DBLP] ISCAS (4), 2003, pp:113-116 [Conf] - Ming Zhang, Naresh R. Shanbhag
**An energy-efficient circuit technique for single event transient noise-tolerance.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 2005, pp:636-639 [Conf] - Lei Wang, Naresh R. Shanbhag
**Noise-tolerant dynamic circuit design.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 1999, pp:549-552 [Conf] - Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
**Low-power distributed arithmetic architectures using nonuniform memory partitioning.**[Citation Graph (0, 0)][DBLP] ISCAS (3), 1999, pp:470-473 [Conf] - Rajamohana Hegde, Naresh R. Shanbhag
**Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI.**[Citation Graph (0, 0)][DBLP] ISCAS (6), 1999, pp:334-337 [Conf] - Mohammad M. Mansour, Naresh R. Shanbhag
**Simplified current and delay models for deep submicron CMOS digital circuits.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2002, pp:109-112 [Conf] - Ganesh Balamurugan, Naresh R. Shanbhag
**Energy-efficient dynamic circuit design in the presence of crosstalk noise.**[Citation Graph (0, 0)][DBLP] ISLPED, 1999, pp:24-29 [Conf] - Rajamohana Hegde, Naresh R. Shanbhag
**Energy-efficient signal processing via algorithmic noise-tolerance.**[Citation Graph (0, 0)][DBLP] ISLPED, 1999, pp:30-35 [Conf] - Manish Goel, Naresh R. Shanbhag
**Low-power adaptive filter architectures via strength reduction.**[Citation Graph (0, 0)][DBLP] ISLPED, 1996, pp:217-220 [Conf] - Manish Goel, Naresh R. Shanbhag
**Dynamic algorithm transformation (DAT) for low-power adaptive signal processing.**[Citation Graph (0, 0)][DBLP] ISLPED, 1997, pp:161-166 [Conf] - Mohammad M. Mansour, Naresh R. Shanbhag
**Low-power VLSI decoder architectures for LDPC codes.**[Citation Graph (0, 0)][DBLP] ISLPED, 2002, pp:284-289 [Conf] - Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer
**A low-power VLSI architecture for turbo decoding.**[Citation Graph (0, 0)][DBLP] ISLPED, 2003, pp:366-371 [Conf] - Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
**Decorrelating (DECOR) transformations for low-power adaptive filters.**[Citation Graph (0, 0)][DBLP] ISLPED, 1998, pp:250-255 [Conf] - Naresh R. Shanbhag
**Lower bounds on power dissipation for DSP algorithms.**[Citation Graph (0, 0)][DBLP] ISLPED, 1996, pp:43-48 [Conf] - Naresh R. Shanbhag, K. Soumyanath, Samuel Martin
**Reliable low-power design in the presence of deep submicron noise (embedded tutorial session).**[Citation Graph (0, 0)][DBLP] ISLPED, 2000, pp:295-302 [Conf] - Srinivasa R. Sridhara, Naresh R. Shanbhag
**A low-power bus design using joint repeater insertion and coding.**[Citation Graph (0, 0)][DBLP] ISLPED, 2005, pp:99-102 [Conf] - Lei Wang, Naresh R. Shanbhag
**Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers.**[Citation Graph (0, 0)][DBLP] ISLPED, 2001, pp:334-339 [Conf] - Girish Varatkar, Naresh R. Shanbhag
**Energy-efficient motion estimation using error-tolerance.**[Citation Graph (0, 0)][DBLP] ISLPED, 2006, pp:113-118 [Conf] - Srinivasa R. Sridhara, Naresh R. Shanbhag, Ganesh Balamurugan
**Joint Equalization and Coding for On-Chip Bus Communication.**[Citation Graph (0, 0)][DBLP] ISQED, 2005, pp:642-647 [Conf] - Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag
**Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1999, pp:358-0 [Conf] - Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
**Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications.**[Citation Graph (0, 0)][DBLP] VLSI Design, 1998, pp:18-23 [Conf] - Srinivasa R. Sridhara, Naresh R. Shanbhag
**Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2005, pp:417-422 [Conf] - Naresh R. Shanbhag
**Reliable and Efficient System-on-Chip Design.**[Citation Graph (0, 0)][DBLP] IEEE Computer, 2004, v:37, n:3, pp:42-50 [Journal] - Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
**Analytical estimation of signal transition activity from word-level statistics.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:718-733 [Journal] - Ming Zhang, Naresh R. Shanbhag
**Soft-Error-Rate-Analysis (SERA) Methodology.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2140-2155 [Journal] - Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer
**Area-efficient high-throughput MAP decoder architectures.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:921-933 [Journal] - Byonghyo Shim, Naresh R. Shanbhag
**Energy-efficient soft error-tolerant digital signal processing.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2006, v:14, n:4, pp:336-348 [Journal] - Byonghyo Shim, Srinivasa R. Sridhara, Naresh R. Shanbhag
**Reliable low-power digital signal processing via reduced precision redundancy.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2004, v:12, n:5, pp:497-510 [Journal] - Srinivasa R. Sridhara, Naresh R. Shanbhag
**Coding for system-on-chip networks: a unified framework.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:655-667 [Journal] - Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, N. J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, S. J. Patel
**Sequential Element Design With Built-In Soft Error Resilience.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1368-1378 [Journal] - Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
**Information-theoretic bounds on average signal transition activity [VLSI systems].**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1999, v:7, n:3, pp:359-368 [Journal] - Manish Goel, Naresh R. Shanbhag
**Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1999, v:7, n:4, pp:463-476 [Journal] - Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj
**A coding framework for low-power address and data busses.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1999, v:7, n:2, pp:212-221 [Journal] - Rajamohana Hegde, Naresh R. Shanbhag
**Toward achieving energy efficiency in presence of deep submicron noise.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:4, pp:379-391 [Journal] - Dilip V. Sarwate, Naresh R. Shanbhag
**High-speed architectures for Reed-Solomon decoders.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:641-655 [Journal] - Rajamohana Hegde, Naresh R. Shanbhag
**Soft digital signal processing.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:813-823 [Journal] - Lei Wang, Naresh R. Shanbhag
**Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:254-269 [Journal] - Mohammad M. Mansour, Naresh R. Shanbhag
**High-throughput LDPC decoders.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:976-996 [Journal] - Lei Wang, Naresh R. Shanbhag
**Low-power MIMO signal processing.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:434-445 [Journal] - Mohammad M. Mansour, Naresh R. Shanbhag
**VLSI architectures for SISO-APP decoders.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:627-650 [Journal] **Stochastic computation.**[Citation Graph (, )][DBLP]**Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip.**[Citation Graph (, )][DBLP]**Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC.**[Citation Graph (, )][DBLP]**Error-resilient low-power Viterbi decoders.**[Citation Graph (, )][DBLP]**Impact of DFE Error Propagation on FEC-Based High-Speed I/O Links.**[Citation Graph (, )][DBLP]**Variation-Tolerant Motion Estimation Architecture.**[Citation Graph (, )][DBLP]**Error-resilient low-power Viterbi decoders via state clustering.**[Citation Graph (, )][DBLP]**Low-power pre-decoding based viterbi decoder for tail-biting convolutional codes.**[Citation Graph (, )][DBLP]**Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard.**[Citation Graph (, )][DBLP]**Computation as estimation: Estimation-theoretic IC design improves robustness and reduces power consumption.**[Citation Graph (, )][DBLP]**The Search for Alternative Computational Paradigms.**[Citation Graph (, )][DBLP]
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