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Uming Ko:
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Publications of Author
- Philippe Royannez, Hugh Mair, Franck Dahan, Mike Wagner, Mark Streeter, Laurent Bouetel, Joel Blasquez, H. Clasen, G. Semino, Julie Dong, D. Scott, B. Pitts, Claudine Raibaut, Uming Ko
A design platform for 90-nm leakage reduction techniques. [Citation Graph (0, 0)][DBLP] DAC, 2005, pp:549-550 [Conf]
- Uming Ko, Mike McMahan, Edgar Auslander
DSP for the Third Generation Wireless Communications. [Citation Graph (0, 0)][DBLP] ICCD, 1999, pp:516-520 [Conf]
- David Li, Andrew Pua, Pranjal Srivastava, Uming Ko
A Repeater Optimization Methodology for Deep Sub-Micron, High Performance Processors. [Citation Graph (0, 0)][DBLP] ICCD, 1997, pp:726-731 [Conf]
- June Jiang, Kan Lu, Uming Ko
High-performance, low-power design techniques for dynamic to static logic interface. [Citation Graph (0, 0)][DBLP] ISLPED, 1997, pp:12-17 [Conf]
- Uming Ko, Poras T. Balsara, Ashwini K. Nanda
Energy optimization of multi-level processor cache architectures. [Citation Graph (0, 0)][DBLP] ISLPD, 1995, pp:45-49 [Conf]
- Uming Ko, Anthony M. Hill, Poras T. Balsara
Design techniques for high performance, energy efficient control logic. [Citation Graph (0, 0)][DBLP] ISLPED, 1996, pp:97-100 [Conf]
- Uming Ko, Andrew Pua, Anthony M. Hill, Pranjal Srivastava
Hybrid dual-threshold design techniques for high-performance processors with low-power features. [Citation Graph (0, 0)][DBLP] ISLPED, 1997, pp:307-311 [Conf]
- Uming Ko, Dinesh G. Patel, Francois J. Henley
Contactless VLSI Laser Probing. [Citation Graph (0, 0)][DBLP] ITC, 1985, pp:930-937 [Conf]
- Uming Ko, Poras T. Balsara
Short-circuit power driven gate sizing technique for reducing power dissipation. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:450-455 [Journal]
- Uming Ko, Poras T. Balsara
High-performance energy-efficient D-flip-flop circuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:94-98 [Journal]
- Uming Ko, T. Balsara, Wai Lee
Low-power design techniques for high-performance CMOS adders. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1995, v:3, n:2, pp:327-333 [Journal]
- Uming Ko, Poras T. Balsara, Ashwini K. Nanda
Energy optimization of multilevel cache architectures for RISC and CISC processors. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:299-308 [Journal]
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