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Rajeev Jayaraman: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen
    Panel: (When) Will FPGAs Kill ASICs? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:321-322 [Conf]
  2. Emil S. Ochotta, Patrick J. Crotty, Charles R. Erickson, Chih-Tsung Huang, Rajeev Jayaraman, Richard C. Li, Joseph D. Linoff, Luan Ngo, Hy V. Nguyen, Kerry M. Pierce, Douglas P. Wieland, Jennifer Zhuang, Scott S. Nance
    A Novel Predictable Segmented FPGA Routing Architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:3-11 [Conf]
  3. Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman
    A Placement Algorithm for FPGA Designs with Multiple I/O Standards. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:211-220 [Conf]
  4. Rajeev Jayaraman, Rob A. Rutenbar
    A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:344-347 [Conf]
  5. Rajeev Jayaraman
    Physical design for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:214-221 [Conf]
  6. Majid Sarrafzadeh, Rajeev Jayaraman
    Guest editorial. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:499-500 [Journal]

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