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Sean Safarpour: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan
    Efficient SAT-based Boolean matching for FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:466-471 [Conf]
  2. Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
    On the relation between simulation-based and SAT-based diagnosis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1139-1144 [Conf]
  3. Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee
    Managing Don't Cares in Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:260-265 [Conf]
  4. Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour
    Diagnosing multiple transition faults in the absence of timing information. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:193-196 [Conf]
  5. Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler
    Utilizing don't care states in SAT-based bounded sequential problems. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:264-269 [Conf]
  6. Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
    Post-verification debugging of hierarchical designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:871-876 [Conf]
  7. Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir
    Debugging sequential circuits using Boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:204-209 [Conf]
  8. Sean Safarpour, Andreas G. Veneris
    Abstraction and Refinement Techniques in Automated Design Debugging. [Citation Graph (0, 0)][DBLP]
    MTV, 2006, pp:88-93 [Conf]
  9. Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler
    Post-Verification Debugging of Hierarchical Designs. [Citation Graph (0, 0)][DBLP]
    MTV, 2005, pp:42-47 [Conf]
  10. Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Freescale Semiconductor, Rolf Drechsler, Alexander Smith
    Debugging Sequential Circuits Using Boolean Satisfiability. [Citation Graph (0, 0)][DBLP]
    MTV, 2004, pp:44-49 [Conf]
  11. Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir
    Maximum circuit activity estimation using pseudo-boolean satisfiability. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1538-1543 [Conf]
  12. Sean Safarpour, Andreas G. Veneris
    Abstraction and refinement techniques in automated design debugging. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1182-1187 [Conf]
  13. Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
    Integrating observability don't cares in all-solution SAT solvers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  14. Trace Compaction using SAT-based Reachability Analysis. [Citation Graph (, )][DBLP]


  15. The day Sherlock Holmes decided to do EDA. [Citation Graph (, )][DBLP]


  16. Improved Design Debugging Using Maximum Satisfiability. [Citation Graph (, )][DBLP]


  17. Towards automated ECOs in FPGAs. [Citation Graph (, )][DBLP]


  18. Spatial and temporal design debug using partial MaxSAT. [Citation Graph (, )][DBLP]


  19. A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. [Citation Graph (, )][DBLP]


  20. Automated silicon debug data analysis techniques for a hardware data acquisition environment. [Citation Graph (, )][DBLP]


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