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Publications of Author

1. Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski, Krishnendu Chakrabarty
   Test cost reduction for SOCs using virtual TAMs and lagrange multipliers. [Citation Graph (0, 0)][DBLP]
   DAC, 2003, pp:738-743 [Conf]
   
2. Anuja Sehgal, Krishnendu Chakrabarty
   Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:422-427 [Conf]
   
3. Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
   Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:285-290 [Conf]
   
4. Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty
   Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores. [Citation Graph (0, 0)][DBLP]
   DATE, 2005, pp:50-55 [Conf]
   
5. Anuja Sehgal, Krishnendu Chakrabarty
   Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2005, pp:88-93 [Conf]
   
6. Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
   TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2003, pp:95-99 [Conf]
   
7. Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
   A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs. [Citation Graph (0, 0)][DBLP]
   ICCD, 2005, pp:137-142 [Conf]
   
8. Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
   IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. [Citation Graph (0, 0)][DBLP]
   ITC, 2004, pp:1203-1212 [Conf]
   
9. Anuja Sehgal, Krishnendu Chakrabarty
   Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2007, v:56, n:1, pp:120-133 [Journal]
   
10. Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
    Test infrastructure design for mixed-signal SOCs with wrapped analog cores. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:292-304 [Journal]
    
11. Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty
    SOC test planning using virtual test access architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1263-1276 [Journal]
    
12. Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty
    Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
    
13. 
    Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. [Citation Graph (, )][DBLP]