The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Polly Siegel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Polly Siegel, Giovanni De Micheli, David L. Dill
    Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:61-67 [Conf]
  2. Polly Siegel, Giovanni De Micheli
    Decomposition methods for library binding of speed-independent asynchronous designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:558-565 [Conf]
  3. Luca Benini, Robin Hodgson, Polly Siegel
    System-level power estimation and optimization. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:173-178 [Conf]
  4. Luca Benini, Polly Siegel, Giovanni De Micheli
    Saving Power by Synthesizing Gated Clocks for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1994, v:11, n:4, pp:32-41 [Journal]
  5. Alan Marshall, Bill Coates, Polly Siegel
    Designing an Asynchronous Communications Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1994, v:11, n:2, pp:8-21 [Journal]

Search in 0.002secs, Finished in 0.002secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002