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Valavan Manohararajah: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
    Incremental retiming for FPGA physical synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:433-438 [Conf]
  2. Valavan Manohararajah, Terry Borer, Stephen Dean Brown, Zvonko G. Vranesic
    Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:232-241 [Conf]
  3. Valavan Manohararajah, Deshanand P. Singh, Stephen Dean Brown
    Post-Placement BDD-Based Decomposition for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:31-38 [Conf]
  4. Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown
    Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:135-142 [Conf]
  5. Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
    Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:3-8 [Conf]
  6. Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
    Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2331-2340 [Journal]
  7. Valavan Manohararajah, Stephen Dean Brown, Zvonko G. Vranesic
    Adaptive FPGAs: High-Level Architecture and a Synthesis Method. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-8 [Conf]
  8. Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown
    Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:895-903 [Journal]

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