Charles H. Stapper Modeling of Integrated Circuit Defect Sensitivities. [Citation Graph (0, 0)][DBLP] IBM Journal of Research and Development, 1983, v:27, n:6, pp:549-557 [Journal]
Charles H. Stapper Modeling of Defects in Integrated Circuit Photolithographic Patterns. [Citation Graph (0, 0)][DBLP] IBM Journal of Research and Development, 1984, v:28, n:4, pp:461-475 [Journal]
Charles H. Stapper Yield Model for Fault Clusters Within Integrated Circuits. [Citation Graph (0, 0)][DBLP] IBM Journal of Research and Development, 1984, v:28, n:5, pp:636-640 [Journal]
Charles H. Stapper Large-Area Fault Clusters and Fault Tolerance in VLSI Circuits: A Review. [Citation Graph (0, 0)][DBLP] IBM Journal of Research and Development, 1989, v:33, n:2, pp:162-173 [Journal]
Charles H. Stapper Simulation of spatial fault distributions for integrated circuit yield estimations. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1314-1318 [Journal]
Charles H. Stapper Statistics associated with spatial fault simulation used for evaluating integrated circuit yield enhancement. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:399-406 [Journal]