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Charles H. Stapper: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Andrzej J. Strojwas, Clark Beck, Dennis Buss, Tülin Erdim Mangir, Charles H. Stapper
    Yield of VLSI circuits: myths vs. reality (panel). [Citation Graph (0, 0)][DBLP]
    DAC, 1986, pp:234-235 [Conf]
  2. Charles H. Stapper, J. A. Patrick, R. J. Rosner
    Yield Model for ASIC and Processor Chips. [Citation Graph (0, 0)][DBLP]
    DFT, 1993, pp:136-143 [Conf]
  3. Charles H. Stapper, A. J. Rideout
    On Fractal Yield Models: A Statistical Paradox. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:83-87 [Conf]
  4. Charles H. Stapper
    A New Statistical Approach for Fault-Tolerant VLSI Systems. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:356-365 [Conf]
  5. Charles H. Stapper
    LSI yield modeling and process monitoring. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2000, v:44, n:1, pp:112-118 [Journal]
  6. Charles H. Stapper
    LSI Yield Modeling and Process Monitoring. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 1976, v:20, n:3, pp:228-234 [Journal]
  7. Charles H. Stapper
    Modeling of Integrated Circuit Defect Sensitivities. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 1983, v:27, n:6, pp:549-557 [Journal]
  8. Charles H. Stapper
    Modeling of Defects in Integrated Circuit Photolithographic Patterns. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 1984, v:28, n:4, pp:461-475 [Journal]
  9. Charles H. Stapper
    Yield Model for Fault Clusters Within Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 1984, v:28, n:5, pp:636-640 [Journal]
  10. Charles H. Stapper
    Large-Area Fault Clusters and Fault Tolerance in VLSI Circuits: A Review. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 1989, v:33, n:2, pp:162-173 [Journal]
  11. Israel Koren, Zahava Koren, Charles H. Stapper
    A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:6, pp:724-734 [Journal]
  12. Charles H. Stapper
    Improved Yield Models for Fault-Tolerant Memory Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:7, pp:872-881 [Journal]
  13. Charles H. Stapper, Hsing-San Lee
    Synergistic Fault-Tolerance for Memory Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:9, pp:1078-1087 [Journal]
  14. Charles H. Stapper
    Simulation of spatial fault distributions for integrated circuit yield estimations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:12, pp:1314-1318 [Journal]
  15. Charles H. Stapper
    Statistics associated with spatial fault simulation used for evaluating integrated circuit yield enhancement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:399-406 [Journal]
  16. Israel Koren, Zahava Koren, Charles H. Stapper
    A statistical study of defect maps of large area VLSI IC's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:249-256 [Journal]

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