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Emrah Acar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Haihua Su, Emrah Acar, Sani R. Nassif
    Power grid reduction based on algebraic multigrid principles. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:109-112 [Conf]
  2. Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi
    A Linear-Centric Simulation Framework for Parametric Fluctuations. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:568-575 [Conf]
  3. Emrah Acar, Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
    S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:60-63 [Conf]
  4. Tao Lin, Emrah Acar, Lawrence T. Pileggi
    h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:19-25 [Conf]
  5. Peng Li, Emrah Acar
    A Waveform Independent Gate Model for Accurate Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:363-365 [Conf]
  6. Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns
    Leakage and leakage sensitivity computation for combinational circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:96-99 [Conf]
  7. Haihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani R. Nassif
    Full chip leakage estimation considering power supply and temperature variations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:78-83 [Conf]
  8. Emrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi
    Time-Domain Simulation of Variational Interconnect Models. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:419-424 [Conf]
  9. Emrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu
    Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:431-436 [Conf]
  10. Ravishankar Arunachalam, Emrah Acar, Sani R. Nassif
    Optimal shielding/spacing metrics for low power design. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:167-172 [Conf]
  11. Emrah Acar, Florentin Dartu, Lawrence T. Pileggi
    TETA: transistor-level waveform evaluation for timing analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:605-616 [Journal]
  12. Emrah Acar, Peter Feldmann
    Simulation of SOI transistor circuits through non-equilibrium initial condition analysis (NEICA). [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  13. Emrah Acar, Kanak Agarwal, Sani R. Nassif
    Characterization of total chip leakage using inverse (reciprocal) gamma distribution. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  14. Sani R. Nassif, Kanak Agarwal, Emrah Acar
    Methods for estimating decoupling capacitance of nonswitching circuit blocks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  15. Peng Li, Zhuo Feng, Emrah Acar
    Characterizing Multistage Nonlinear Drivers and Variability for Accurate Timing and Noise Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1205-1214 [Journal]
  16. Emrah Acar, Anirudh Devgan, Sani R. Nassif
    Leakage and Leakage Sensitivity Computation for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:2, pp:172-181 [Journal]

  17. Performance modeling for early analysis of multi-core systems. [Citation Graph (, )][DBLP]

  18. Yield estimation of SRAM circuits using "Virtual SRAM Fab". [Citation Graph (, )][DBLP]

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