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Hsiao-Pin Su: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
    A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:262-267 [Conf]
  2. Tzu-Chieh Tien, Hsiao-Pin Su, Yu-Wen Tsay, Yih-Chih Chou, Youn-Long Lin
    Integrating logic retiming and register placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:136-139 [Conf]
  3. Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
    Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:12-17 [Conf]
  4. Hsiao-Pin Su, Youn-Long Lin
    A phase assignment method for virtual-wire-based hardware emulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:776-783 [Journal]
  5. Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin
    A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:475-483 [Journal]

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