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Daehyun Kim: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Taeweon Suh, Daehyun Kim, Hsien-Hsin S. Lee
    Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:553-558 [Conf]
  2. Amol Ghoting, Gregory Buehrer, Srinivasan Parthasarathy, Daehyun Kim, Anthony Nguyen, Yen-Kuang Chen, Pradeep Dubey
    A Characterization of Data Mining Workloads on a Modern Processor. [Citation Graph (0, 0)][DBLP]
    DaMoN, 2005, pp:- [Conf]
  3. Daehyun Kim, Mainak Chaudhuri, Mark Heinrich
    Leveraging cache coherence in active memory systems. [Citation Graph (0, 0)][DBLP]
    ICS, 2002, pp:2-13 [Conf]
  4. Daehyun Kim, Mainak Chaudhuri, Mark Heinrich
    Active Memory Techniques for ccNUMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:10- [Conf]
  5. Mainak Chaudhuri, Daehyun Kim, Mark Heinrich
    Cache Coherence Protocol Design for Active Memory Systems. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2002, pp:83-89 [Conf]
  6. Amol Ghoting, Gregory Buehrer, Srinivasan Parthasarathy, Daehyun Kim, Anthony Nguyen, Yen-Kuang Chen, Pradeep Dubey
    Cache-conscious Frequent Pattern Mining on a Modern Processor. [Citation Graph (0, 0)][DBLP]
    VLDB, 2005, pp:577-588 [Conf]
  7. Daehyun Kim, Mainak Chaudhuri, Mark Heinrich, Evan Speight
    Architectural Support for Uniprocessor and Multiprocessor Active Memory Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:3, pp:288-307 [Journal]
  8. Amol Ghoting, Gregory Buehrer, Srinivasan Parthasarathy, Daehyun Kim, Anthony Nguyen, Yen-Kuang Chen, Pradeep Dubey
    Cache-conscious frequent pattern mining on modern and emerging processors. [Citation Graph (0, 0)][DBLP]
    VLDB J., 2007, v:16, n:1, pp:77-96 [Journal]
  9. Christopher J. Hughes, Radek Grzeszczuk, Eftychios Sifakis, Daehyun Kim, Sanjeev Kumar, Andrew Selle, Jatin Chhugani, Matthew J. Holliman, Yen-Kuang Chen
    Physical simulation for animation and visual effects: parallelization and characterization for chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:220-231 [Conf]
  10. Seongmin Noh, Daehyun Kim, Vu-Duc Ngo, Hae-Wook Choi
    Performance and Complexity Analysis of Credit-Based End-to-End Flow Control in Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    ISPA, 2007, pp:268-277 [Conf]

  11. Efficient pattern mining on shared memory systems: implications for chip multiprocessor architectures. [Citation Graph (, )][DBLP]


  12. Static text region detection in video sequences using color and orientation consistencies. [Citation Graph (, )][DBLP]


  13. Atomic Vector Operations on Chip Multiprocessors. [Citation Graph (, )][DBLP]


  14. Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU. [Citation Graph (, )][DBLP]


  15. Scaling performance of interior-point method on large-scale chip multiprocessor system. [Citation Graph (, )][DBLP]


  16. Fast sort on CPUs and GPUs: a case for bandwidth oblivious SIMD sort. [Citation Graph (, )][DBLP]


  17. Second Life and the New Generation of Virtual Worlds. [Citation Graph (, )][DBLP]


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