The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Suphachai Sutanthavibul: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Suphachai Sutanthavibul, Eugene Shragowitz
    An Adaptive Timing-Driven Layout for High Speed VLSI. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:90-95 [Conf]
  2. Suphachai Sutanthavibul, Eugene Shragowitz
    Dynamic Prediction of Critical Paths and Nets for Constructive Timing-Driven Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:632-635 [Conf]
  3. Suphachai Sutanthavibul, Eugene Shragowitz, J. Ben Rosen
    An Analytical Approach to Floorplan Design and Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:187-192 [Conf]
  4. H. Chang, Eugene Shragowitz, Jian Liu, Habib Youssef, Bing Lu, Suphachai Sutanthavibul
    Net criticality revisited: an effective method to improve timing in physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:155-160 [Conf]
  5. Habib Youssef, Eugene Shragowitz, Suphachai Sutanthavibul
    Prelayout timing analysis of cell-based VLSI designs. [Citation Graph (0, 0)][DBLP]
    Computer-Aided Design, 1992, v:24, n:7, pp:367-379 [Journal]
  6. Suphachai Sutanthavibul, Eugene Shragowitz, Rung-Bin Lin
    An adaptive timing-driven placement for high performance VLSIs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1488-1498 [Journal]
  7. Suphachai Sutanthavibul, Eugene Shragowitz, J. Ben Rosen
    An analytical approach to floorplan design and optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:6, pp:761-769 [Journal]

Search in 0.014secs, Finished in 0.014secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002