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Himanshu Kaul: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dennis Sylvester, Himanshu Kaul
    Future Performance Challenges in Nanometer Design. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:3-8 [Conf]
  2. Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin
    DVS for On-Chip Bus Designs Based on Timing Error Correction. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:80-85 [Conf]
  3. Himanshu Kaul, Dennis Sylvester
    A novel buffer circuit for energy efficient signaling in dual-VDD systems. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:462-467 [Conf]
  4. Himanshu Kaul, Dennis Sylvester, David Blaauw
    Active shields: a new approach to shielding global wires. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:112-117 [Conf]
  5. Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif
    Power-aware global signaling strategies. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:604-607 [Conf]
  6. Himanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy
    Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:194-199 [Conf]
  7. Himanshu Kaul, Dennis Sylvester
    Transition Aware Global Signaling (TAGS). [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:53-0 [Conf]
  8. Himanshu Kaul, Dennis Sylvester, David Blaauw
    Active shielding of RLC global interconnects. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:98-104 [Conf]
  9. Dennis Sylvester, Himanshu Kaul
    Power-Driven Challenges in Nanometer Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:6, pp:12-22 [Journal]
  10. Himanshu Kaul, Dennis Sylvester
    Low-power on-chip communication based on transition-aware global signaling (TAGS). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:5, pp:464-476 [Journal]
  11. Himanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy
    Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:11, pp:1225-1238 [Journal]
  12. Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin
    DVS for On-Chip Bus Designs Based on Timing Error Correction [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  13. A robust alternate repeater technique for high performance busses in the multi-core era. [Citation Graph (, )][DBLP]


  14. A robust edge encoding technique for energy-efficient multi-cycle interconnect. [Citation Graph (, )][DBLP]


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