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Hiran Tennakoon: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hiran Tennakoon, Carl Sechen
    Efficient and accurate gate sizing with piecewise convex delay models. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:807-812 [Conf]
  2. Hiran Tennakoon, Carl Sechen
    Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:395-402 [Conf]

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