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Shashidhar Thakur: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shashidhar Thakur, D. F. Wong, Shankar Krishnamoorthy
    Delay Minimal Decomposition of Multiplexers in Technology Mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:254-257 [Conf]
  2. Shashidhar Thakur, D. F. Wong
    On Designing ULM-based FPGA Logic Modules. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:3-9 [Conf]
  3. Shashidhar Thakur, D. F. Wong
    Universal Logic Modules for Series-Parallel Functions. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:31-37 [Conf]
  4. Yao-Wen Chang, Shashidhar Thakur, Kai Zhu, D. F. Wong
    A new global routing algorithm for FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:356-361 [Conf]
  5. Shashidhar Thakur, D. F. Wong
    Simultaneous area and delay minimum K-LUT mapping for K-exact networks. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:402-408 [Conf]
  6. Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong
    An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:207-210 [Conf]
  7. Jinan Lou, Shashidhar Thakur, Shankar Krishnamoorthy, Henry S. Sheng
    Estimating routing congestion using probabilistic analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:32-41 [Journal]
  8. Shashidhar Thakur, Yao-Wen Chang, Martin D. F. Wong, S. Muthukrishnan
    Algorithms for an FPGA switch module routing problem with application to global routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:32-46 [Journal]
  9. Shashidhar Thakur, D. F. Wong
    Series-parallel functions and FPGA logic module design. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:1, pp:102-122 [Journal]

  10. Algorithms for a switch module routing problem. [Citation Graph (, )][DBLP]

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