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Sybille Hellebrand: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska
    STARBIST: Scan Autocorrelated Random Pattern Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:472-477 [Conf]
  2. Sybille Hellebrand, Hans-Joachim Wunderlich, Vyacheslav N. Yarmolik
    Symmetric Transparent BIST for RAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:702-707 [Conf]
  3. Vyacheslav N. Yarmolik, Sybille Hellebrand, Hans-Joachim Wunderlich
    Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:173-179 [Conf]
  4. Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich
    Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:185-190 [Conf]
  5. Vyacheslav N. Yarmolik, I. V. Bykov, Sybille Hellebrand, Hans-Joachim Wunderlich
    Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms. [Citation Graph (0, 0)][DBLP]
    EDCC, 1999, pp:339-350 [Conf]
  6. Sybille Hellebrand, Hans-Joachim Wunderlich
    Synthesis of Self-Testable Controllers. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:580-585 [Conf]
  7. Sybille Hellebrand, Hans-Joachim Wunderlich
    Automatisierung des Entwurfs vollständig testbarer Schaltungen. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung (2), 1988, pp:145-159 [Conf]
  8. Sybille Hellebrand, Birgit Reeb, Steffen Tarnick, Hans-Joachim Wunderlich
    Pattern generation for a deterministic BIST scheme. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:88-94 [Conf]
  9. Sybille Hellebrand, Hans-Joachim Wunderlich
    An efficient procedure for the synthesis of fast self-testable controller structures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:110-116 [Conf]
  10. Sybille Hellebrand, Steffen Tarnick, Bernard Courtois, Janusz Rajski
    Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:120-129 [Conf]
  11. Sybille Hellebrand, Hans-Joachim Wunderlich
    The Pseudo-Exhaustive Test of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:19-27 [Conf]
  12. Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig
    Mixed-Mode BIST Using Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:195-204 [Conf]
  13. Sybille Hellebrand, Hans-Joachim Wunderlich, Huaguo Liang
    A mixed mode BIST scheme based on reseeding of folding counters. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:778-784 [Conf]
  14. Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich
    Two-dimensional test data compression for scan-based deterministic BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:894-902 [Conf]
  15. Armin Würtenberger, Christofer S. Tautermann, Sybille Hellebrand
    A Hybrid Coding Strategy For Optimized Test Data Compression. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:451-459 [Conf]
  16. Armin Würtenberger, Christofer S. Tautermann, Sybille Hellebrand
    Data Compression for Multiple Scan Chains Using Dictionaries with Corrections. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:926-935 [Conf]
  17. Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik
    Error Detecting Refreshment for Embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:384-390 [Conf]
  18. Andre Hertwig, Sybille Hellebrand, Hans-Joachim Wunderlich
    Fast Self-Recovering Controllers. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:296-302 [Conf]
  19. Sybille Hellebrand, Hans-Joachim Wunderlich, Andre Hertwig
    Synthesizing Fast, Online-Testable Control Units. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:4, pp:36-41 [Journal]
  20. Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wunderlich
    A Mixed-Mode BIST Scheme Based on Folding Compression. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2002, v:17, n:2, pp:203-212 [Journal]
  21. Sybille Hellebrand, Janusz Rajski, Steffen Tarnick, Srikanth Venkataraman, Bernard Courtois
    Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:2, pp:223-233 [Journal]
  22. Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik
    Efficient Online and Offline Testing of Embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:7, pp:801-809 [Journal]
  23. Hans-Joachim Wunderlich, Sybille Hellebrand
    The pseudoexhaustive test of sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:1, pp:26-33 [Journal]
  24. Philipp Öhler, Sybille Hellebrand, Hans-Joachim Wunderlich
    An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:91-96 [Conf]
  25. Bernd Becker, Ilia Polian, Sybille Hellebrand, Bernd Straube, Hans-Joachim Wunderlich
    DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems). [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2006, v:48, n:5, pp:304-0 [Journal]

  26. A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction. [Citation Graph (, )][DBLP]


  27. Are Robust Circuits Really Robust? [Citation Graph (, )][DBLP]


  28. Tools and devices supporting the pseudo-exhaustive test. [Citation Graph (, )][DBLP]


  29. A Modular Memory BIST for Optimized Memory Repair. [Citation Graph (, )][DBLP]


  30. Verification and Analysis of Self-Checking Properties through ATPG. [Citation Graph (, )][DBLP]


  31. ATPG-based grading of strong fault-secureness. [Citation Graph (, )][DBLP]


  32. Signature Rollback - A Technique for Testing Robust Circuits. [Citation Graph (, )][DBLP]


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