The SCEAS System
Navigation Menu

Search the dblp DataBase


Keith A. Bowman: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. James Tschanz, Keith A. Bowman, Vivek De
    Variation-tolerant circuits: circuit solutions and techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:762-763 [Conf]
  2. Peter Suaris, Taeho Kgil, Keith A. Bowman, Vivek De, Trevor N. Mudge
    Total power-optimal pipelining and parallel processing under process variations in nanometer technology. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:535-540 [Conf]
  3. Ali Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De
    Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:26-29 [Conf]
  4. Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl
    Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:167-172 [Conf]
  5. Keith A. Bowman, James Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De
    Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:79-84 [Conf]
  6. Keith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar
    Tutorial II: Variability and Its Impact on Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:5- [Conf]
  7. Jeffrey A. Davis, Raguraman Venkatesan, Keith A. Bowman, James D. Meindl
    Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session). [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:147-148 [Conf]
  8. Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James Tschanz, Vivek De
    Comparative Analysis of Conventional and Statistical Design Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:238-243 [Conf]
  9. Osman S. Unsal, James Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin
    Impact of Parameter Variations on Circuits and Microarchitecture. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:6, pp:30-39 [Journal]
  10. Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl
    A minimum total power methodology for projecting limits on CMOS GSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:235-251 [Journal]
  11. Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl
    Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:899-912 [Journal]

  12. Circuit techniques for dynamic variation tolerance. [Citation Graph (, )][DBLP]

  13. Resilient circuits - Enabling energy-efficient performance and reliability. [Citation Graph (, )][DBLP]

  14. Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors. [Citation Graph (, )][DBLP]

  15. Resilient microprocessor design for high performance & energy efficiency. [Citation Graph (, )][DBLP]

Search in 0.418secs, Finished in 0.419secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002