Search the dblp DataBase
Hsiao-Ping Tseng :
[Publications ]
[Author Rank by year ]
[Co-authors ]
[Prefers ]
[Cites ]
[Cited by ]
Publications of Author
Hsiao-Ping Tseng , Louis Scheffer , Carl Sechen Timing and Crosstalk Driven Area Routing. [Citation Graph (0, 0)][DBLP ] DAC, 1998, pp:378-381 [Conf ] Le-Chin Eugene Liu , Hsiao-Ping Tseng , Carl Sechen Chip-level area routing. [Citation Graph (0, 0)][DBLP ] ISPD, 1998, pp:197-204 [Conf ] Hsiao-Ping Tseng , Carl Sechen A gridless multilayer router for standard cell circuits using CTMcells. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:10, pp:1462-1479 [Journal ] Hsiao-Ping Tseng , Louis Scheffer , Carl Sechen Timing- and crosstalk-driven area routing. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:528-544 [Journal ] A gridless multi-layer router for standard cell circuits using CTM cells. [Citation Graph (, )][DBLP ] Search in 0.001secs, Finished in 0.001secs