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Jeffrey A. Davis: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Raguraman Venkatesan, Jeffrey A. Davis, James D. Meindl
    A physical model for the transient response of capacitively loaded distributed rlc interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:763-766 [Conf]
  2. Ajay Joshi, Jeffrey A. Davis
    Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:446-451 [Conf]
  3. Vinita V. Deodhar, Jeffrey A. Davis
    Voltage scaling and repeater insertion for high-throughput low-power interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:349-352 [Conf]
  4. Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl
    Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:167-172 [Conf]
  5. Vinita V. Deodhar, Jeffrey A. Davis
    Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:592-597 [Conf]
  6. Pranav Anbalagan, Jeffrey A. Davis
    Maximum multiplicity distributions (MMD). [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:107-113 [Conf]
  7. Pranav Anbalagan, Jeffrey A. Davis
    A priori prediction of tightly clustered connections based on heuristic classification trees. [Citation Graph (0, 0)][DBLP]
    SLIP, 2006, pp:9-15 [Conf]
  8. Jeffrey A. Davis, Raguraman Venkatesan, Keith A. Bowman, James D. Meindl
    Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session). [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:147-148 [Conf]
  9. Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl
    Prediction of interconnect fan-out distribution using Rent's rule. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:107-112 [Conf]
  10. Ajay Joshi, Jeffrey A. Davis
    A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI). [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:64-68 [Conf]
  11. James W. Joyner, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
    Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures. [Citation Graph (0, 0)][DBLP]
    SLIP, 2000, pp:123-127 [Conf]
  12. Pranav Anbalagan, Jeffrey A. Davis
    Maximum Multiplicity Distributions for Length Prediction Driven Placement. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:981-0 [Conf]
  13. Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis
    Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:773-776 [Conf]
  14. James D. Meindl, Jeffrey A. Davis, Payman Zarkesh-Ha, Chirag S. Patel, Kevin P. Martin, Paul A. Kohl
    Interconnect opportunities for gigascale integration. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:245-264 [Journal]
  15. Vinita V. Deodhar, Jeffrey A. Davis
    Optimization of throughput performance for low-power VLSI interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:308-318 [Journal]
  16. Ajay Joshi, Jeffrey A. Davis
    Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:899-910 [Journal]
  17. Ajay Joshi, Gerald G. Lopez, Jeffrey A. Davis
    Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:990-1002 [Journal]
  18. Qiang Chen, Jeffrey A. Davis, Payman Zarkesh-Ha, James D. Meindl
    A compact physical via blockage model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:689-692 [Journal]
  19. Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
    Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:6, pp:649-659 [Journal]
  20. James W. Joyner, Raguraman Venkatesan, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl
    Impact of three-dimensional architectures on interconnects in gigascale integration. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:922-928 [Journal]
  21. Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl
    Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI). [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:899-912 [Journal]

  22. IntSim: A CAD tool for optimization of multilevel interconnect networks. [Citation Graph (, )][DBLP]


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