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Publications of Author

1. Ajay K. Verma, Paolo Ienne
   Towards the automatic exploration of arithmetic-circuit architectures. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:445-450 [Conf]
   
2. Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay K. Verma
   Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:218-223 [Conf]
   
3. Paolo Ienne, Ajay K. Verma
   Arithmetic Transformations to Maximise the Use of Compressor Trees. [Citation Graph (0, 0)][DBLP]
   DELTA, 2004, pp:219-224 [Conf]
   
4. Ajay K. Verma, Paolo Ienne
   Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2004, pp:791-798 [Conf]
   
5. Ajay K. Verma, Philip Brisk, Paolo Ienne
   Rethinking custom ISE identification: a new processor-agnostic method. [Citation Graph (0, 0)][DBLP]
   CASES, 2007, pp:125-134 [Conf]
   
6. Philip Brisk, Ajay K. Verma, Paolo Ienne
   An optimistic and conservative register assignment heuristic for chordal graphs. [Citation Graph (0, 0)][DBLP]
   CASES, 2007, pp:209-217 [Conf]
   
7. Ajay K. Verma, Philip Brisk, Paolo Ienne
   Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. [Citation Graph (0, 0)][DBLP]
   DAC, 2007, pp:404-409 [Conf]
   
8. Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Parandeh-Afshar
   Enhancing FPGA Performance for Arithmetic Circuits. [Citation Graph (0, 0)][DBLP]
   DAC, 2007, pp:334-337 [Conf]
   
9. Ajay K. Verma, Paolo Ienne
   Automatic synthesis of compressor trees: reevaluating large counters. [Citation Graph (0, 0)][DBLP]
   DATE, 2007, pp:443-448 [Conf]
   
10. 
    Challenges in Automatic Optimization of Arithmetic Circuits. [Citation Graph (, )][DBLP]
    
    
11. 
    Hybrid LZA: a near optimal implementation of the leading zero anticipator. [Citation Graph (, )][DBLP]
    
    
12. 
    Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. [Citation Graph (, )][DBLP]
    
    
13. 
    Fast, quasi-optimal, and pipelined instruction-set extensions. [Citation Graph (, )][DBLP]
    
    
14. 
    Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. [Citation Graph (, )][DBLP]
    
    
15. 
    Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. [Citation Graph (, )][DBLP]
    
    
16. 
    Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. [Citation Graph (, )][DBLP]
    
    
17. 
    Iterative layering: Optimizing arithmetic circuits by structuring the information flow. [Citation Graph (, )][DBLP]
    
    
18. 
    Arithmetic optimization for custom instruction set synthesis. [Citation Graph (, )][DBLP]