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Bart Vermeulen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Bart Vermeulen, Mohammad Z. Urfianto, Sandeep Kumar Goel
    Automatic generation of breakpoint hardware for silicon debug. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:514-517 [Conf]
  2. Erik Jan Marinissen, Bart Vermeulen, Robert Madge, Michael Kessler, Michael Müller
    Creating Value Through Test. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10402-10409 [Conf]
  3. Sandeep Kumar Goel, Bart Vermeulen
    Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1103-1110 [Conf]
  4. Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen
    Optimal Interconnect ATPG Under a Ground-Bounce Constraint. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:369-378 [Conf]
  5. Gert-Jan van Rootselaar, Bart Vermeulen
    Silicon debug: scan chains alone are not enough. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:892-902 [Conf]
  6. Bart Vermeulen
    TAPS All Over My Chips! So Now What Do I Do? [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1190- [Conf]
  7. Bart Vermeulen, Camelia Hora, Bram Kruseman, Erik Jan Marinissen, Robert Van Rijsinge
    Trends in Testing Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:688-697 [Conf]
  8. Bart Vermeulen, Steven Oostdijk, Frank Bouwman
    Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:121-130 [Conf]
  9. Bart Vermeulen, Tom Waayers, Sjaak Bakker
    EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:55-63 [Conf]
  10. Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel
    Core-Based Scan Architecture for Silicon Debug. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:638-647 [Conf]
  11. Fidel Muradali, Mike Ricchetti, Bart Vermeulen, Bulent I. Dervisoglu, Bob Gottlieb, Bernd Koenemann, C. J. Clark
    Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer? [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:445-446 [Conf]
  12. Erik Jan Marinissen, Bart Vermeulen, Henk D. L. Hollmann, Ben Bennetts
    Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:2, pp:8-18 [Journal]
  13. Bart Vermeulen, Sandeep Kumar Goel
    Design for Debug: Catching Design Errors in Digital Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:3, pp:37-45 [Journal]
  14. Bart Vermeulen, Kees Goossens, Remco van Steeden, Martijn T. Bennebroek
    Communication-Centric SoC Debug Using Transactions. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:69-76 [Conf]
  15. Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek
    Transaction-Based Communication-Centric Debug. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:95-106 [Conf]
  16. Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen
    Optimal Interconnect ATPG Under a Ground-Bounce Constraint. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:1, pp:17-31 [Journal]

  17. A Run-Time Memory Protection Methodology. [Citation Graph (, )][DBLP]


  18. You can catch more bugs with transaction level honey. [Citation Graph (, )][DBLP]


  19. A high-level debug environment for communication-centric debug. [Citation Graph (, )][DBLP]


  20. INDEXYS, a Logical Step beyond GENESYS. [Citation Graph (, )][DBLP]


  21. A distributed architecture to check global properties for post-silicon debug. [Citation Graph (, )][DBLP]


  22. New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism. [Citation Graph (, )][DBLP]


  23. Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip. [Citation Graph (, )][DBLP]


  24. Overview of Debug Standardization Activities. [Citation Graph (, )][DBLP]


  25. Functional Debug Techniques for Embedded Systems. [Citation Graph (, )][DBLP]


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