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Sandeep Kumar Goel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Bart Vermeulen, Mohammad Z. Urfianto, Sandeep Kumar Goel
    Automatic generation of breakpoint hardware for silicon debug. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:514-517 [Conf]
  2. Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke
    Fault detection and diagnosis with parity trees for space compaction of test responses. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1095-1098 [Conf]
  3. Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, Steven Oostdijk
    Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:108-113 [Conf]
  4. Sandeep Kumar Goel, Erik Jan Marinissen
    Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10738-10741 [Conf]
  5. Sandeep Kumar Goel, Erik Jan Marinissen
    On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:44-49 [Conf]
  6. Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
    Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:285-290 [Conf]
  7. Sandeep Kumar Goel, Erik Jan Marinissen
    Effective and Efficient Test Architecture Design for SOCs. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:529-538 [Conf]
  8. Sandeep Kumar Goel, Bart Vermeulen
    Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1103-1110 [Conf]
  9. Vikram Iyengar, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
    Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:1159-1168 [Conf]
  10. Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty
    IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1203-1212 [Conf]
  11. Bart Vermeulen, Tom Waayers, Sandeep Kumar Goel
    Core-Based Scan Architecture for Silicon Debug. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:638-647 [Conf]
  12. Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel
    Wrapper design for embedded core test. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:911-920 [Conf]
  13. Sandeep Kumar Goel, Erik Jan Marinissen
    Cluster-Based Test Architecture Design for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:259-264 [Conf]
  14. Bart Vermeulen, Sandeep Kumar Goel
    Design for Debug: Catching Design Errors in Digital Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:3, pp:37-45 [Journal]
  15. Sandeep Kumar Goel, Erik Jan Marinissen
    SOC test architecture design for efficient utilization of test bandwidth. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:399-429 [Journal]
  16. Sandeep Kumar Goel, Maurice Meijer, José Pineda de Gyvez
    Testing and Diagnosis of Power Switches in SOCs. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:145-150 [Conf]
  17. Sandeep Kumar Goel, Erik Jan Marinissen
    On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  18. Test-architecture optimization for TSV-based 3D stacked ICs. [Citation Graph (, )][DBLP]


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