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Ashok Vittal: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ashok Vittal, Malgorzata Marek-Sadowska
    Minimal Delay Interconnect Design Using Alphabetic Trees. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:392-396 [Conf]
  2. Ashok Vittal, Malgorzata Marek-Sadowska
    Power Optimal Buffered Clock Tree Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:497-502 [Conf]
  3. Ashok Vittal, Malgorzata Marek-Sadowska
    Power Distribution Topology Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:503-507 [Conf]
  4. Ashok Vittal, Hein Ha, Forrest Brewer, Malgorzata Marek-Sadowska
    Clock skew optimization for ground bounce control. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:395-399 [Conf]
  5. Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang
    Modeling Crosstalk in Resistive VLSI Interconnections. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:470-475 [Conf]
  6. Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang
    Crosstalk in VLSI interconnections. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1817-1824 [Journal]
  7. Ashok Vittal, Malgorzata Marek-Sadowska
    Crosstalk reduction for VLSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:290-298 [Journal]
  8. Ashok Vittal, Malgorzata Marek-Sadowska
    Low-power buffered clock tree design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:965-975 [Journal]

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