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Friedrich Hapke: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Harald P. E. Vranken, Sandeep Kumar Goel, Andreas Glowatz, Jürgen Schlöffel, Friedrich Hapke
    Fault detection and diagnosis with parity trees for space compaction of test responses. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1095-1098 [Conf]
  2. Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
    PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:212-217 [Conf]
  3. Valentin Gherman, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Michael Garbers
    Efficient Pattern Mapping for Deterministic Logic BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:48-56 [Conf]
  4. Yuyi Tang, Hans-Joachim Wunderlich, Harald P. E. Vranken, Friedrich Hapke, Michael Wittke, Piet Engelke, Ilia Polian, Bernd Becker
    X-Masking During Logic BIST and Its Impact on Defect Coverage. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:442-451 [Conf]
  5. Harald P. E. Vranken, Friedrich Hapke, Soenke Rogge, Domenico Chindamo, Erik H. Volkerink
    ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1069-1078 [Conf]
  6. Yuyi Tang, Hans-Joachim Wunderlich, Piet Engelke, Ilia Polian, Bernd Becker, Jürgen Schlöffel, Friedrich Hapke, Michael Wittke
    X-masking during logic BIST and its impact on defect coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:2, pp:193-202 [Journal]
  7. Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel
    Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2007, pp:181-187 [Conf]

  8. Experimental Studies on SAT-Based ATPG for Gate Delay Faults. [Citation Graph (, )][DBLP]


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