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Publications of Author

1. Jörg A. Walter, Jens Leenstra, Gerhard Döttling, Bernd Leppla, Hans-Jürgen Münster, Kevin W. Kark, Bruce Wile
   Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors. [Citation Graph (0, 0)][DBLP]
   DAC, 1997, pp:89-94 [Conf]
   
2. Nicolas Mäding, Jens Leenstra, Juergen Pille, R. Sautter, S. Büttner, S. Ehrenreich, W. Haller
   The vector fixed point unit of the synergistic processor element of the cell architecture processor. [Citation Graph (0, 0)][DBLP]
   DATE Designers' Forum, 2006, pp:244-248 [Conf]
   
3. Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schünemann, Thomas Schwarz, Hans-Joachim Wunderlich
   Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability. [Citation Graph (0, 0)][DBLP]
   ITC, 2001, pp:461-469 [Conf]
   
4. Jens Leenstra, Lambert Spaanenburg
   On the Design and Test of Asynchronous Macros Embedded in Synchronous Systems. [Citation Graph (0, 0)][DBLP]
   ITC, 1989, pp:838-845 [Conf]
   
5. Jens Leenstra, Lambert Spaanenburg
   Hierarchical Test Program Development for Scan Testable Circuits. [Citation Graph (0, 0)][DBLP]
   ITC, 1991, pp:375-384 [Conf]
   
6. David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel
   Custom circuit design as a driver of microprocessor performance. [Citation Graph (0, 0)][DBLP]
   IBM Journal of Research and Development, 2000, v:44, n:6, pp:799-822 [Journal]
   
7. Michael E. Imhof, Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mäding, Jens Leenstra
   Scan Test Planning for Power Reduction. [Citation Graph (0, 0)][DBLP]
   DAC, 2007, pp:521-526 [Conf]
   
8. Joachim Fenkes, Tobias Gemmeke, Jens Leenstra
   Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process. [Citation Graph (0, 0)][DBLP]
   J. Low Power Electronics, 2007, v:3, n:1, pp:54-59 [Journal]
   
9. 
   Scan chain clustering for test power reduction. [Citation Graph (, )][DBLP]