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Wei-Shen Wang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Wei-Shen Wang, Vladik Kreinovich, Michael Orshansky
    Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:161-166 [Conf]
  2. Wei-Shen Wang, Michael Orshansky
    Robust estimation of parametric yield under limited descriptions of uncertainty. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:884-890 [Conf]
  3. Michael Liu, Wei-Shen Wang, Michael Orshansky
    Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:2-7 [Conf]
  4. Bin Zhang, Wei-Shen Wang, Michael Orshansky
    FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:755-760 [Conf]
  5. Michael Orshansky, Wei-Shen Wang, Martine Ceberio, Gang Xiang
    Interval-based robust statistical techniques for non-negative convex functions, with application to timing analysis of computer chips. [Citation Graph (0, 0)][DBLP]
    SAC, 2006, pp:1645-1649 [Conf]
  6. Wei-Shen Wang, Michael Liu, Michael Orshansky
    Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:1-7 [Journal]
  7. Wei-Shen Wang, Michael Orshansky
    Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2007, v:3, n:1, pp:1-12 [Journal]

  8. Statistical analysis of circuit timing using majorization. [Citation Graph (, )][DBLP]


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