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Bill Underwood: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Thomas W. Williams, Bill Underwood, M. Ray Mercer
    The Interdependence Between Delay-Optimization of Synthesized Networks and Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:87-92 [Conf]
  2. Sungho Kang, Wai-on Law, Bill Underwood
    Path-Delay Fault Simulation for a Standard Scan Design Methodology. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:359-362 [Conf]
  3. Steven P. Smith, Bill Underwood, Joe Newman
    An Analysis of Parallel Logic Simulation on Several Architectures. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:65-68 [Conf]
  4. Rhonda Kay Gaede, M. Ray Mercer, Bill Underwood
    Calculation of Greatest Lower Bounds Obtainable by the Cutting Algorithm. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:498-505 [Conf]
  5. Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer
    Delay Testing Quality in Timing-Optimized Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:897-905 [Conf]
  6. John Salick, Bill Underwood, M. Ray Mercer
    Built-In Self Test Input Generator for Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:115-125 [Conf]
  7. Steven P. Smith, Bill Underwood, M. Ray Mercer
    D^3FS: A Demand Driven Deductive Fault Simulator. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:582-592 [Conf]
  8. Bill Underwood, Jack Ferguson
    The Parallel-Test-Detect Fault Simulation Algorithm. [Citation Graph (0, 0)][DBLP]
    ITC, 1989, pp:712-717 [Conf]
  9. Bill Underwood, Wai-on Law, Sungho Kang, Haluk Konuk
    Fastpath: A Path-Delay Test Generator for Standard Scan Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1994, pp:154-163 [Conf]
  10. Bill Underwood, M. Ray Mercer
    Correlating Testability with Fault Detection. [Citation Graph (0, 0)][DBLP]
    ITC, 1984, pp:697-704 [Conf]
  11. Bruce D. Cory, Rohit Kapur, Bill Underwood
    Speed Binning with Path Delay Test in 150-nm Technology. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:41-45 [Journal]

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