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Publications of Author

1. Michael J. Wirthlin, Brian McMurtrey
   IP delivery for FPGAs using Applets and JHDL. [Citation Graph (0, 0)][DBLP]
   DAC, 2002, pp:2-7 [Conf]
   
2. Matthew French, Li Wang, Tyler Anderson, Michael J. Wirthlin
   Post Synthesis Level Power Modeling of FPGAs. [Citation Graph (0, 0)][DBLP]
   FCCM, 2005, pp:281-282 [Conf]
   
3. Michael J. Wirthlin, Brad L. Hutchings
   A dynamic instruction set computer. [Citation Graph (0, 0)][DBLP]
   FCCM, 1995, pp:99-109 [Conf]
   
4. Michael J. Wirthlin, Eric Johnson, Nathan Rollins, Michael Caffrey, Paul Graham
   The Reliability of FPGA Circuit Designs in the Presence of Radiation Induced Configuration Upsets. [Citation Graph (0, 0)][DBLP]
   FCCM, 2003, pp:133-142 [Conf]
   
5. Michael J. Wirthlin, Steve Morrison, Paul Graham, Brian Bray
   Improving the Performance and Efficiency of an Adaptive Amplification Operation Using Configurable Hardware. [Citation Graph (0, 0)][DBLP]
   FCCM, 2000, pp:267-278 [Conf]
   
6. Matthew French, Li Wang, Michael J. Wirthlin
   Power Visualization, Analysis, and Optimization Tools for FPGAs. [Citation Graph (0, 0)][DBLP]
   FCCM, 2006, pp:185-194 [Conf]
   
7. Michael J. Wirthlin, Welson Sun
   DSynth: A Pipeline Synthesis Environment for FPGAs. [Citation Graph (0, 0)][DBLP]
   FCCM, 2006, pp:343-344 [Conf]
   
8. Welson Sun, Michael J. Wirthlin, Stephen Neuendorffer
   Combining module selection and resource sharing for efficient FPGA pipeline synthesis. [Citation Graph (0, 0)][DBLP]
   FPGA, 2006, pp:179-188 [Conf]
   
9. Mike Wirthlin, Misha Burich, Andrew Guyler, Brian Von Herzen
   High-level languages: the future or a passing fad? [Citation Graph (0, 0)][DBLP]
   FPGA, 2007, pp:127- [Conf]
   
10. Michael J. Wirthlin
    Improving the reliability of FPGA circuits using triple-modular redundancy (TMR) & efficient voter placement. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:252- [Conf]
    
11. Michael J. Wirthlin, Paul Graham
    Improving the performance and efficiency of an adaptive amplification operation using configurable hardware (poster abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:219- [Conf]
    
12. Michael J. Wirthlin, Brad L. Hutchings
    Sequencing Run-Time Reconfigured Hardware with Software. [Citation Graph (0, 0)][DBLP]
    FPGA, 1996, pp:122-128 [Conf]
    
13. Michael J. Wirthlin, Brad L. Hutchings
    Improving Functional Density Through Run-Time Constant Propagation. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:86-92 [Conf]
    
14. Brad L. Hutchings, Michael J. Wirthlin
    Implementation Approaches for Reconfigurable Logic Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 1995, pp:419-428 [Conf]
    
15. Wesley J. Landaker, Michael J. Wirthlin, Brad L. Hutchings
    Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:806-815 [Conf]
    
16. Michael J. Wirthlin, Brad L. Hutchings, Carl Worth
    Synthesizing RTL Hardware from Java Byte Codes. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:123-132 [Conf]
    
17. Michael J. Wirthlin, Brian McMurtrey
    Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:555-564 [Conf]
    
18. Toomas P. Plaks, Philip Leong, Michael J. Wirthlin
    Mobile Computing Architectures, Design and Implementation. [Citation Graph (0, 0)][DBLP]
    HICSS, 2005, pp:- [Conf]
    
19. Maya Gokhale, Paul Graham, Eric Johnson, Nathan Rollins, Michael J. Wirthlin
    Dynamic Reconfiguration for Management of Radiation-Induced Faults in FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
    
20. Michael J. Wirthlin
    Senior-Level Embedded Systems Design Project Using FPGAs. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:91-92 [Conf]
    
21. Michael J. Wirthlin, Navaneethan Sundaramoorthy
    Measuring the Routing Costs of FPGA Circuit Components. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
    
22. Brad L. Hutchings, Brent E. Nelson, Michael J. Wirthlin
    Designing and Debugging Custom Computing Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:1, pp:20-28 [Journal]
    
23. Edward A. Lee, Stephen Neuendorffer, Michael J. Wirthlin
    Actor-Oriented Design of Embedded Hardware and Software Systems. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2003, v:12, n:3, pp:231-260 [Journal]
    
24. Michael J. Wirthlin, Brian McMurtrey
    Web-based IP evaluation and distribution using applets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:985-994 [Journal]
    
25. Michael J. Wirthlin, Brad L. Hutchings
    Improving functional density using run-time circuit reconfiguration [FPGAs]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:247-256 [Journal]
    
26. 
    TMR with More Frequent Voting for Improved FPGA Reliability. [Citation Graph (, )][DBLP]
    
    
27. 
    Design Productivity for Configurable Computing. [Citation Graph (, )][DBLP]
    
    
28. 
    An Introduction to Radiation-Induced Failure Modes and Related Mitigation Methods For Xilinx SRAM FPGAs. [Citation Graph (, )][DBLP]
    
    
29. 
    On-Orbit Flight Results from the Reconfigurable Cibola Flight Experiment Satellite (CFESat). [Citation Graph (, )][DBLP]
    
    
30. 
    Voter insertion algorithms for FPGA designs using triple modular redundancy. [Citation Graph (, )][DBLP]
    
    
31. 
    FPGA partial reconfiguration via configuration scrubbing. [Citation Graph (, )][DBLP]
    
    
32. 
    Bitstream compression through frame removal and partial reconfiguration. [Citation Graph (, )][DBLP]
    
    
33. 
    A multi-layered XML schema and design tool for reusing and integrating FPGA IP. [Citation Graph (, )][DBLP]
    
    
34. 
    Noise impact of single-event upsets on an FPGA-based digital filter. [Citation Graph (, )][DBLP]