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John A. Waicukauski: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Peter Wohl, John A. Waicukauski, Sanjay Patel
    Scalable selector architecture for x-tolerant deterministic BIST. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:934-939 [Conf]
  2. Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin
    Efficient compression and application of deterministic patterns in a logic BIST architecture. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:566-569 [Conf]
  3. Peter Wohl, John A. Waicukauski, Sanjay Patel, Gregory A. Maston
    Effective diagnostics through interval unloads in a BIST environment. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:249-254 [Conf]
  4. Miron Abramovici, B. Krishnamurthy, A. Mathews, B. Rogers, M. Schulz, S. Seth, John A. Waicukauski
    What is the Path to Fast Fault Simulation? [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:183-192 [Conf]
  5. Y. Arzoumanian, John A. Waicukauski
    Fault Diagnosis in an LSSD Environment. [Citation Graph (0, 0)][DBLP]
    ITC, 1981, pp:86-88 [Conf]
  6. Vishal Jain, John A. Waicukauski
    Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:148-153 [Conf]
  7. Franco Motika, John A. Waicukauski, Edward B. Eichelberger, Eric Lindbloom
    An LSSD Pseudo Random Pattern Test System. [Citation Graph (0, 0)][DBLP]
    ITC, 1983, pp:283-288 [Conf]
  8. Bejoy G. Oomman, Wu-Tung Cheng, John A. Waicukauski
    A Universal Technique for Accelerating Simulation of Scan Test Patterns. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:135-141 [Conf]
  9. John A. Waicukauski, Eric Lindbloom
    Fault Detection Effectiveness of Weighted Random Patterns. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:245-255 [Conf]
  10. John A. Waicukauski, Eric Lindbloom, Edward B. Eichelberger, Donato O. Forlenza, Tim McCarthy
    A Statistical Calculation of Fault Detection Probabilities By Fast Fault Simulation. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:779-784 [Conf]
  11. John A. Waicukauski, Eric Lindbloom, Vijay S. Iyengar, Barry K. Rosen
    Transition Fault Simulation by Parallel Pattern Single Fault Propagation. [Citation Graph (0, 0)][DBLP]
    ITC, 1986, pp:542-551 [Conf]
  12. Peter Wohl, John A. Waicukauski
    Optimizing the flattened test-generation model for very large designs. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:681-690 [Conf]
  13. Peter Wohl, John A. Waicukauski
    Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:13-20 [Conf]
  14. Peter Wohl, John A. Waicukauski
    A Unified Interface for Scan Test Generation Based on STIL. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:1011-1019 [Conf]
  15. Peter Wohl, John A. Waicukauski
    Extracting gate-level networks from simulation tables. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:622-631 [Conf]
  16. Peter Wohl, John A. Waicukauski
    Defining ATPG rules checking in STIL. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:971-979 [Conf]
  17. Peter Wohl, John A. Waicukauski
    Using Verilog simulation libraries for ATPG. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1011-1020 [Conf]
  18. Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin
    X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:727-736 [Conf]
  19. Peter Wohl, John A. Waicukauski, Thomas W. Williams
    Design of compactors for signature-analyzers in built-in self-test. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:54-63 [Conf]
  20. Nadime Zacharia, Janusz Rajski, Jerzy Tyszer, John A. Waicukauski
    Two-Dimensional Test Data Decompressor for Multiple Scan Designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:186-194 [Conf]
  21. Peter Wohl, John A. Waicukauski
    Using ATPG for clock rules checking in complex scan design. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:130-136 [Conf]
  22. Peter Wohl, John A. Waicukauski, Matthew Graf
    Testing "untestable" faults in three-state circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:324-331 [Conf]
  23. Peter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew
    Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:359-365 [Conf]
  24. Peter Wohl, John A. Waicukauski, Rohit Kapur, S. Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini
    Minimizing the Impact of Scan Compression. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:67-74 [Conf]
  25. Peter Wohl, A. Waicukauski, Sanjay Patel
    Automated Design and Insertion of Optimal One-Hot Bus Encoders. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:409-415 [Conf]
  26. John A. Waicukauski, Eric Lindbloom, Edward B. Eichelberger, Orazio P. Forlenza
    A Method for Generating Weighted Random Test Patterns. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 1989, v:33, n:2, pp:149-161 [Journal]
  27. Vijay S. Iyengar, Barry K. Rosen, John A. Waicukauski
    On computing the sizes of detected delay faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:3, pp:299-312 [Journal]

  28. Fully X-tolerant, very high scan compression. [Citation Graph (, )][DBLP]


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