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Pu Liu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan
    A systematic method for functional unit power estimation in microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:554-557 [Conf]
  2. Madhusudhan Govindaraju, Aleksander Slominski, Kenneth Chiu, Pu Liu, Robert van Engelen, Michael J. Lewis
    Toward Characterizing the Performance of SOAP Toolkits. [Citation Graph (0, 0)][DBLP]
    GRID, 2004, pp:365-372 [Conf]
  3. Pu Liu, Zhenyu Qi, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang
    Fast thermal simulation for architecture level dynamic thermal management. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:639-644 [Conf]
  4. Pu Liu, Sheldon X.-D. Tan, Hang Li, Zhenyu Qi, Jun Kong, Bruce McGaughy, Lei He
    An efficient method for terminal reduction of interconnect circuits considering delay variations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:821-826 [Conf]
  5. Hang Li, Pu Liu, Zhenyu Qi, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang
    Efficient Thermal Simulation for Run-Time Temperature Tracking and Management. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:130-136 [Conf]
  6. Pu Liu, Michael J. Lewis
    Mobile Code Enabled Web Services. [Citation Graph (0, 0)][DBLP]
    ICWS, 2005, pp:167-174 [Conf]
  7. Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan
    Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:603-608 [Conf]
  8. Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu
    Compact Reduced Order Modeling for Multiple-Port Interconnects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:413-418 [Conf]
  9. Boyuan Yan, Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy
    Passive Modeling of Interconnects by Waveform Shaping. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:356-361 [Conf]
  10. Pu Liu, Francis C. M. Lau, Michael J. Lewis, Cho-Li Wang
    A New Asynchronous Parallel Evolutionary Algorithm for Function Optimization. [Citation Graph (0, 0)][DBLP]
    PPSN, 2002, pp:401-410 [Conf]
  11. Michael R. Head, Madhusudhan Govindaraju, Aleksander Slominski, Pu Liu, Nayef Abu-Ghazaleh, Robert van Engelen, Kenneth Chiu, Michael J. Lewis
    A Benchmark Suite for SOAP-based Communication in Grid Web Services. [Citation Graph (0, 0)][DBLP]
    SC, 2005, pp:19- [Conf]
  12. Jiandong Li, Zhuo Kang, Yan Li, Hongqing Cao, Pu Liu
    Automatic Data Mining by Asynchronous Parallel Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    TOOLS (39), 2001, pp:99-107 [Conf]
  13. Yan Li, Lishan Kang, Hugo de Garis, Zhuo Kang, Pu Liu
    A Robust Algorithm for Solving Nonlinear Programming Problems. [Citation Graph (0, 0)][DBLP]
    Int. J. Comput. Math., 2002, v:79, n:5, pp:523-536 [Journal]
  14. Zhenyu Qi, Hao Yu, Pu Liu, Sheldon X.-D. Tan, Lei He
    Wideband passive multiport model order reduction and realization of RLCM circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:8, pp:1496-1509 [Journal]
  15. Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy
    SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:158-161 [Conf]
  16. Pu Liu, Michael J. Lewis
    Uniform Dynamic Deployment of Web and Grid Services. [Citation Graph (0, 0)][DBLP]
    ICWS, 2007, pp:26-34 [Conf]
  17. Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan
    Efficient power modeling and software thermal sensing for runtime temperature monitoring. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]

  18. Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form. [Citation Graph (, )][DBLP]


  19. FEKIS: a fast architecture-level thermal analyzer for online thermal regulation. [Citation Graph (, )][DBLP]


  20. Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks. [Citation Graph (, )][DBLP]


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