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Hua Xiang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hua Xiang, D. F. Wong, Xiaoping Tang
    An algorithm for integrated pin assignment and buffer planning. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:584-589 [Conf]
  2. Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu
    A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:470-477 [Conf]
  3. Peilin Jiang, Hua Xiang, Fuji Ren, Shingo Kuroiwa
    An Advanced Mental State Transition Network and Psychological Experiments. [Citation Graph (0, 0)][DBLP]
    EUC, 2005, pp:1026-1035 [Conf]
  4. Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun
    Wire type assignment for FPGA routing. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:61-67 [Conf]
  5. Xiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong
    A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:49-56 [Conf]
  6. Hua Xiang, Kai-Yuan Chao, D. F. Wong
    ECO algorithms for removing overlaps between power rails and signal wires. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:67-74 [Conf]
  7. Hua Xiang, Xiaoping Tang, D. F. Wong
    An Algorithm for Simultaneous Pin Assignment and Routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:232-0 [Conf]
  8. Hua Xiang, Xiaoping Tang, Martin D. F. Wong
    Bus-Driven Floorplanning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:66-73 [Conf]
  9. Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri
    Wire density driven global routing for CMP variation and timing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:487-492 [Conf]
  10. Hua Xiang, Kai-Yuan Chao, D. F. Wong
    An ECO algorithm for eliminating crosstalk violations. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:41-46 [Conf]
  11. Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
    Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:181-186 [Conf]
  12. Hua Xiang, I-Min Liu, Martin D. F. Wong
    Wire Planning with Bounded Over-the-Block Wires. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:622-627 [Conf]
  13. Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. Wong
    OPC-Friendly Bus Driven Floorplanning. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:847-852 [Conf]
  14. Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu
    A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:141-147 [Journal]
  15. Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
    An ECO routing algorithm for eliminating coupling-capacitance violations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1754-1762 [Journal]
  16. Hua Xiang, Xiaoping Tang, Martin D. F. Wong
    Min-cost flow-based algorithm for simultaneous pin assignment and routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:870-878 [Journal]
  17. Hua Xiang, Xiaoping Tang, Martin D. F. Wong
    Bus-driven floorplanning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:11, pp:1522-1530 [Journal]
  18. Hua Xiang, Xiaoping Tang, Martin D. F. Wong
    An algorithm for integrated pin assignment and buffer planning. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:3, pp:561-572 [Journal]
  19. Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan
    TROY: Track Router with Yield-driven Wire Planning. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:55-58 [Conf]
  20. Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong
    Is your layout density verification exact?: a fast exact algorithm for density calculation. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:19-26 [Conf]
  21. Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong
    Dummy fill density analysis with coupling constraints. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:3-10 [Conf]
  22. Peilin Jiang, Hua Xiang, Fuji Ren, Shingo Kuroiwa, Nanning Zheng
    The Framework of Mental State Transition Analysis. [Citation Graph (0, 0)][DBLP]
    MICAI, 2007, pp:1046-1055 [Conf]

  23. Coupling-aware Dummy Metal Insertion for Lithography. [Citation Graph (, )][DBLP]


  24. History-based VLSI legalization using network flow. [Citation Graph (, )][DBLP]


  25. Logical and physical restructuring of fan-in trees. [Citation Graph (, )][DBLP]


  26. Communication avoiding Gaussian elimination. [Citation Graph (, )][DBLP]


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