|
Search the dblp DataBase
Natesan Venkateswaran:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- Jinjun Xiong, Vladimir Zolotov, Natesan Venkateswaran, Chandu Visweswariah
Criticality computation in parameterized statistical timing. [Citation Graph (0, 0)][DBLP] DAC, 2006, pp:63-68 [Conf]
- Kanad Chakraborty, Natesan Venkateswaran
Congestion Mitigation During Placement. [Citation Graph (0, 0)][DBLP] Great Lakes Symposium on VLSI, 1999, pp:228-229 [Conf]
- Matthew R. Guthaus, Natesan Venkateswaran, Vladimir Zolotov, Dennis Sylvester, Richard B. Brown
Optimization objectives and models of variation for statistical gate sizing. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2005, pp:313-316 [Conf]
- Matthew R. Guthaus, Natesan Venkateswaran, Chandu Visweswariah, Vladimir Zolotov
Gate sizing using incremental parameterized statistical timing analysis. [Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:1029-1036 [Conf]
- Natesan Venkateswaran, Dinesh Bhatia
Clock-Skew Constrained Cell Placement. [Citation Graph (0, 0)][DBLP] VLSI Design, 1996, pp:146-149 [Conf]
Search in 0.002secs, Finished in 0.003secs
|