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Chao-Yang Yeh: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chao-Yang Yeh, Malgorzata Marek-Sadowska
    Delay budgeting in sequential circuit with application on FPGA placement. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:202-207 [Conf]
  2. Chao-Yang Yeh, Malgorzata Marek-Sadowska
    Skew-programmable clock design for FPGA and skew-aware placement. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:33-40 [Conf]
  3. Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai
    A sliding window scheme for accurate clock mesh analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:939-946 [Conf]
  4. Chao-Yang Yeh, Malgorzata Marek-Sadowska
    Minimum-Area Sequential Budgeting for FPGA. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:813-817 [Conf]
  5. Chao-Yang Yeh, Malgorzata Marek-Sadowska
    Timing-aware power noise reduction in layout. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:627-634 [Conf]
  6. Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai
    Clock Distribution Architectures: A Comparative Study. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:85-91 [Conf]
  7. Chao-Yang Yeh, Malgorzata Marek-Sadowska
    Sequential delay budgeting with interconnect prediction. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:23-30 [Conf]
  8. Chao-Yang Yeh, Malgorzata Marek-Sadowska
    Sequential delay budgeting with interconnect prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1028-1037 [Journal]

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