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Gary S. Ditlow: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. D. A. Zein, O. P. Engel, Gary S. Ditlow
    HLSIM - A New Hierarchical Logic Simulator and Netlist Converter. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:432-437 [Conf]
  2. Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu (Jerry) Qi, Mircea R. Stan
    Structured and tuned array generation (STAG) for high-performance random logic. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:257-262 [Conf]
  3. Gary S. Ditlow, Anshul Gupta, Richard Moore, David Moran, Ralph Williams, Tom Wilkins
    Parallel Analysis of IC Power Distribution Networks. [Citation Graph (0, 0)][DBLP]
    PPSC, 1999, pp:- [Conf]
  4. Jacob Savir, Gary S. Ditlow, Paul H. Bardell
    Random Pattern Testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:1, pp:79-90 [Journal]

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