The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Wayne Burleson: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zheng Zhou, Wayne Burleson
    Equivalence Checking of Datapaths Based on Canonical Arithmetic Expressions. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:546-551 [Conf]
  2. Wayne Burleson, Prashant Jain, Subramanian Venkatraman
    Dynamically Parameterized Architectures for Power-Aware Video Coding: Motion Estimation and DCT. [Citation Graph (0, 0)][DBLP]
    Workshop on Digital and Computational Video, 2001, pp:4-12 [Conf]
  3. Atul Maheshwari, Israel Koren, Wayne Burleson
    Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:597-0 [Conf]
  4. S. R. Park, Wayne Burleson
    Configuration Cloning: Exploiting Regularity in Dynamic DSP Architectures. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:81-89 [Conf]
  5. Sriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne Burleson
    A dynamically reconfigurable adaptive viterbi decoder. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:227-236 [Conf]
  6. Atul Maheshwari, Wayne Burleson
    Repeater and current-sensing hybrid circuits for on-chip interconnects. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:269-272 [Conf]
  7. Aiyappan Natarajan, David Jasinski, Wayne Burleson, Russell Tessier
    A hybrid adiabatic content addressable memory for ultra low-power applications. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:72-75 [Conf]
  8. Vishak Venkatraman, Atul Maheshwari, Wayne Burleson
    Mitigating static power in current-sensed interconnects. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:224-229 [Conf]
  9. Wayne Burleson
    Using Regular Array Methods for DSP Module Synthesis. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:58-67 [Conf]
  10. Guy Gogniat, Tilman Wolf, Wayne Burleson
    Reconfigurable Security Support for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    HICSS, 2006, pp:- [Conf]
  11. Wayne Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems
    The Spring Scheduling Co-Processor: A Scheduling Accelerator. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:140-144 [Conf]
  12. Walter B. Marvin, Wayne Burleson
    A Simulator for General Purpose Optical Arrays. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:486-489 [Conf]
  13. Andrew Laffely, Jian Liang, Russell Tessier, Wayne Burleson
    Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2003, pp:105-108 [Conf]
  14. J. Peden, Wayne Burleson, C. Leonardo
    The Multimedia Online Collaboration Architecture: Tools to Enable Distance Learning. [Citation Graph (0, 0)][DBLP]
    IEEE International Conference on Multimedia and Expo (II), 2000, pp:593-596 [Conf]
  15. Lilian Bossuet, Wayne Burleson, Guy Gogniat, Vikas Anand, Andrew Laffely, Jean Luc Philippe
    Targeting Tiled Architectures in Design Exploration. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:172- [Conf]
  16. Lilian Bossuet, Guy Gogniat, Wayne Burleson
    Dynamically Configurable Security for SRAM FPGA Bitstreams. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  17. Wayne Burleson, L. W. Cotten, Fabian Klass, Maciej J. Ciesielski
    Forum: Wave-pipelining: Is it Practical? [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:163-166 [Conf]
  18. Yongjin Jeong, Wayne Burleson
    High-Level Estimation of High-Performance Architectures for Reed-Solomon Decoding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:720-723 [Conf]
  19. Bongjin Jung, Wayne Burleson
    A VLSI Systolic Array Architecture for Lempel-Ziv-Based Data Compression. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:65-68 [Conf]
  20. J. David Narkiewicz, Wayne Burleson
    Rank-order Filtering Algorithms: A Comparison of VLSI Implementations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1941-1944 [Conf]
  21. Ankireddy Nalamalpu, Wayne Burleson
    Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:204-211 [Conf]
  22. Atul Maheshwari, Wayne Burleson, Russell Tessier
    Trading off Reliability and Power-Consumption in Ultra-low Power Systems. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:361-366 [Conf]
  23. Vishak Venkatraman, Wayne Burleson
    Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:522-527 [Conf]
  24. Jinwook Jang, Sheng Xu, Wayne Burleson
    Jitter in Deep Sub-Micron Interconnect. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:84-89 [Conf]
  25. Aiyappan Natarajan, Vijay Shankar, Atul Maheshwari, Wayne Burleson
    Sensing Design Issues in Deep Submicron CMOS SRAMs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:42-45 [Conf]
  26. Srividya Srinivasaraghavan, Wayne Burleson
    Interconnect Effort - A Unification of Repeater Insertion and Logical Effort. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:55-61 [Conf]
  27. Wayne Burleson, Sheng Xu
    Digital Systems Design with ASIC and FPGA: A Novel Course Using CD/DVD and On-Line Formats. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:3-4 [Conf]
  28. Andrew Laffely, Wayne Burleson
    Using System On-A-Chip As A Vehicle For VLSI Design Education. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:148-149 [Conf]
  29. Jeongseon Euh, Wayne Burleson
    Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering. [Citation Graph (0, 0)][DBLP]
    PACS, 2000, pp:51-64 [Conf]
  30. Jeongseon Euh, Jeevan Chittamuru, Wayne Burleson
    A Low-Power Content-Adaptive Texture Mapping Architecture for Real-Time 3D Graphics. [Citation Graph (0, 0)][DBLP]
    PACS, 2002, pp:99-109 [Conf]
  31. Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems, Wayne Burleson, Jason Ko
    The Spring Scheduling Co-Processor: Design, Use, and Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1993, pp:106-111 [Conf]
  32. Guy Gogniat, Wayne Burleson, Lilian Bossuet
    Configurable Computing for High-Security/High-Performance Ambient Systems. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:72-81 [Conf]
  33. Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne Burleson
    NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:69-75 [Conf]
  34. Vishak Venkatraman, Wayne Burleson
    Impact of Process Variations on Multi-Level Signaling for On-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:362-367 [Conf]
  35. Atul Maheshwari, Wayne Burleson, Russell Tessier
    Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:299-311 [Journal]
  36. Atul Maheshwari, Wayne Burleson
    Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:11, pp:1239-1244 [Journal]

  37. Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering. [Citation Graph (, )][DBLP]


  38. A monitor interconnect and support subsystem for multicore processors. [Citation Graph (, )][DBLP]


  39. High-efficiency protection solution for off-chip memory in embedded systems. [Citation Graph (, )][DBLP]


  40. Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators. [Citation Graph (, )][DBLP]


  41. Low-power clock distribution in a multilayer core 3d microprocessor. [Citation Graph (, )][DBLP]


  42. Analysis and mitigation of NBTI-impact on PVT variability in repeated global interconnect performance. [Citation Graph (, )][DBLP]


  43. MOLES: Malicious off-chip leakage enabled by side-channels. [Citation Graph (, )][DBLP]


  44. Leakage-based differential power analysis (LDPA) on sub-90nm CMOS cryptosystems. [Citation Graph (, )][DBLP]


  45. Low-power sub-threshold design of secure physical unclonable functions. [Citation Graph (, )][DBLP]


  46. On temperature planarization effect of copper dummy fills in deep nanometer technology. [Citation Graph (, )][DBLP]


  47. Temperature effects on energy optimization in sub-threshold circuit design. [Citation Graph (, )][DBLP]


Search in 0.005secs, Finished in 0.007secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002