The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Johannes Schemmel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Markus Loose, Karlheinz Meier, Johannes Schemmel
    Entwicklung einer Kamera mit adaptiven Photorezeptoren in analoger CMOS-Technologie. [Citation Graph (0, 0)][DBLP]
    DAGM-Symposium, 1996, pp:301-312 [Conf]
  2. Jörg Langeheine, Joachim Becker, Simon Fölling, Karlheinz Meier, Johannes Schemmel
    A Cmos Fpta Chip For Intrinsic Hardware Evolution Of Analog Electronic Circuits. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2001, pp:172-175 [Conf]
  3. Jörg Langeheine, Karlheinz Meier, Johannes Schemmel
    Intrinsic Evolution of Quasi DC Solutions for Transistor Level Analog Electronic Circuits Using a CMOS FPTA Chip. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2002, pp:75-84 [Conf]
  4. Jörg Langeheine, Karlheinz Meier, Johannes Schemmel, Martin Trefzer
    Intrinsic Evolution of Digital-to-Analog Converters Using a CMOS FPTA Chip. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2004, pp:18-25 [Conf]
  5. Felix Schürmann, Steffen G. Hohmann, Johannes Schemmel, Karlheinz Meier
    Towards an Artificial Neural Network Framework. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2002, pp:266-273 [Conf]
  6. Martin Trefzer, Jörg Langeheine, Johannes Schemmel, Karlheinz Meier
    New Genetic Operators to Facilitate Understanding of Evolved Transistor Circuits. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2004, pp:217-224 [Conf]
  7. Steffen G. Hohmann, Johannes Schemmel, Felix Schürmann, Karlheinz Meier
    Exploring The Parameter Space Of A Genetic Algorithm For Training An Analog Neural Network. [Citation Graph (0, 0)][DBLP]
    GECCO, 2002, pp:375-382 [Conf]
  8. Jörg Langeheine, Martin Trefzer, Daniel Brüderle, Karlheinz Meier, Johannes Schemmel
    On the Evolution of Analog Electronic Circuits Using Building Blocks on a CMOS FPTA. [Citation Graph (0, 0)][DBLP]
    GECCO (1), 2004, pp:1316-1327 [Conf]
  9. Jörg Langeheine, Joachim Becker, Simon Fölling, Karlheinz Meier, Johannes Schemmel
    Initial Studies of a New VLSI Field Programmable Transistor Array. [Citation Graph (0, 0)][DBLP]
    ICES, 2001, pp:62-73 [Conf]
  10. Jörg Langeheine, Simon Fölling, Karlheinz Meier, Johannes Schemmel
    Towards a Silicon Primordial Soup: A Fast Approach to Hardware Evolution with a VLSI Transistor Array. [Citation Graph (0, 0)][DBLP]
    ICES, 2000, pp:123-132 [Conf]
  11. Johannes Schemmel, Karlheinz Meier, Felix Schürmann
    A VLSI Implementation of an Analog Neural Network Suited for Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    ICES, 2001, pp:50-61 [Conf]
  12. Tillmann Schmitz, Steffen G. Hohmann, Karlheinz Meier, Johannes Schemmel, Felix Schürmann
    Speeding up Hardware Evolution: A Coprocessor for Evolutionary Algorithms. [Citation Graph (0, 0)][DBLP]
    ICES, 2003, pp:274-285 [Conf]
  13. Martin Trefzer, Jörg Langeheine, Karlheinz Meier, Johannes Schemmel
    Operational Amplifiers: An Example for Multi-objective Optimization on an Analog Evolvable Hardware Platform. [Citation Graph (0, 0)][DBLP]
    ICES, 2005, pp:86-97 [Conf]
  14. Felix Schürmann, Karlheinz Meier, Johannes Schemmel
    Edge of Chaos Computation in Mixed-Mode VLSI - A Hard Liquid. [Citation Graph (0, 0)][DBLP]
    NIPS, 2004, pp:- [Conf]
  15. Johannes Fieres, Karlheinz Meier, Johannes Schemmel
    A Convolutional Neural Network Tolerant of Synaptic Faults for Low-Power Analog Hardware. [Citation Graph (0, 0)][DBLP]
    ANNPR, 2006, pp:122-132 [Conf]
  16. Martin Trefzer, Jörg Langeheine, Karlheinz Meier, Johannes Schemmel
    A Modular Framework for the Evolution of Circuits on Configurable Transistor Array Architectures. [Citation Graph (0, 0)][DBLP]
    AHS, 2006, pp:32-42 [Conf]
  17. Johannes Schemmel, Daniel Brüderle, Karlheinz Meier, Boris Ostendorf
    Modeling Synaptic Plasticity within Networks of Highly Accelerated I&F Neurons. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3367-3370 [Conf]
  18. Daniel Brüderle, Andreas Grübl, Karlheinz Meier, Eilif Mueller, Johannes Schemmel
    A Software Framework for Tuning the Dynamics of Neuromorphic Silicon Towards Biology. [Citation Graph (0, 0)][DBLP]
    IWANN, 2007, pp:479-486 [Conf]
  19. Stefan Philipp, Andreas Grübl, Karlheinz Meier, Johannes Schemmel
    Interconnecting VLSI Spiking Neural Networks Using Isochronous Connections. [Citation Graph (0, 0)][DBLP]
    IWANN, 2007, pp:471-478 [Conf]

  20. Training convolutional networks of threshold neurons suited for low-power hardware implementation. [Citation Graph (, )][DBLP]


  21. Implementing Synaptic Plasticity in a VLSI Spiking Neural Network Model. [Citation Graph (, )][DBLP]


  22. Wafer-scale integration of analog neural networks. [Citation Graph (, )][DBLP]


  23. Realizing biological spiking network models in a configurable wafer-scale hardware system. [Citation Graph (, )][DBLP]


Search in 0.003secs, Finished in 0.004secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002