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Erno Salminen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tero Arpinen, Petri Kukkala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen
    Configurable multiprocessor platform with RTOS for distributed execution of UML 2.0 designed applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1324-1329 [Conf]
  2. Ari Kulmala, Erno Salminen, Olli Lehtoranta, Timo D. Hämäläinen, Marko Hännikäinen
    Impact of Shared Instruction Memory on Performance of FPGA-based MP-SoC Video Encoder. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:59-64 [Conf]
  3. Ari Kulmala, Erno Salminen, Timo D. Hämäläinen
    Instruction Memory Architecture Evaluation on Multiprocessor FPGA MPEG-4 Encoder. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:105-110 [Conf]
  4. Antti Rasmus, Ari Kulmala, Erno Salminen, Timo D. Hämäläinen
    IP Integration Overhead Analysis in System-on-Chip Video Encoder. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:333-336 [Conf]
  5. Olli Lehtoranta, Erno Salminen, Ari Kulmala, Marko Hännikäinen, Timo D. Hämäläinen
    A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:380-385 [Conf]
  6. Vesa Lahtinen, Erno Salminen, Kimmo Kuusilinna, Timo D. Hämäläinen
    Comparison of synthesized bus and crossbar interconnection architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:433-436 [Conf]
  7. Erno Salminen, Timo D. Hämäläinen, Tero Kangas, Kimmo Kuusilinna, Jukka Saarinen
    Interfacing multiple processors in a system-on-chip video encoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:478-481 [Conf]
  8. Jouni Riihimäki, Erno Salminen, Kimmo Kuusilinna, Timo Hämäläinen
    Parameter optimization tool for enhancing on-chip network performance. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:61-64 [Conf]
  9. Erno Salminen, Tero Kangas, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna, Timo D. Hämäläinen
    Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:354-363 [Conf]
  10. Tero Kangas, Jouni Riihimäki, Erno Salminen, Vesa Lahtinen, Heikki Orsila, Kimmo Kuusilinna, Timo D. Hämäläinen
    A Communication-Centric Design Flow for HIBI-Based SoCs. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:474-483 [Conf]
  11. Erno Salminen, Vesa Lahtinen, Tero Kangas, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen
    HIBI v.2 Communication Network for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:413-422 [Conf]
  12. Tero Kangas, Petri Kukkala, Heikki Orsila, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen, Jouni Riihimäki, Kimmo Kuusilinna
    UML-based multiprocessor SoC design framework. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:2, pp:281-320 [Journal]
  13. Ari Kulmala, Erno Salminen, Timo D. Hämäläinen
    Evaluating Large System-on-Chip on Multi-FPGA Platform. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2007, pp:179-189 [Conf]
  14. Cristian Grecu, André Ivanov, Partha Pratim Pande, Axel Jantsch, Erno Salminen, Ümit Y. Ogras, Radu Marculescu
    Towards Open Network-on-Chip Benchmarks. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:205- [Conf]
  15. Erno Salminen, Tero Kangas, Vesa Lahtinen, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen
    Benchmarking mesh and hierarchical bus networks in system-on-chip context. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:8, pp:477-488 [Journal]
  16. Heikki Orsila, Tero Kangas, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen
    Automated memory-aware application distribution for Multi-processor System-on-Chips. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:11, pp:795-815 [Journal]
  17. Erno Salminen, Tero Kangas, Timo D. Hämäläinen, Jouni Riihimäki, Vesa Lahtinen, Kimmo Kuusilinna
    HIBI Communication Network for System-on-Chip. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:43, n:2-3, pp:185-205 [Journal]

  18. Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA. [Citation Graph (, )][DBLP]


  19. On network-on-chip comparison. [Citation Graph (, )][DBLP]


  20. Evaluating the Model Accuracy in Automated Design Space Exploration. [Citation Graph (, )][DBLP]


  21. HIBI-based multiprocessor SoC on FPGA. [Citation Graph (, )][DBLP]


  22. Modeling Embedded Software Platforms with a UML Profile. [Citation Graph (, )][DBLP]


  23. Evaluating SoC Network Performance in MPEG-4 Encoder. [Citation Graph (, )][DBLP]


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