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Serge Bernard: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell
    Implementation of a linear histogram BIST for ADCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:590-595 [Conf]
  2. Yves Bertrand, Marie-Lise Flottes, Florence Azaïs, Serge Bernard, Laurent Latorre, Regis Lorival
    European Network for Test Education. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:230-234 [Conf]
  3. Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell
    Analog BIST Generator for ADC Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:338-346 [Conf]
  4. Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell
    On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2001, pp:425-436 [Conf]
  5. Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell
    A New Methodology For ADC Test Flow Optimization. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:201-209 [Conf]
  6. Michel Renovell, Jean Marc Galliere, Florence Azaïs, Serge Bernard, Yves Bertrand
    Boolean and current detection of MOS transistor with gate oxide short. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:1039-1048 [Conf]
  7. Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell
    A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:266-271 [Conf]
  8. Michel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand
    Hardware Resource Minimization for Histogram-Based ADC BIST. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:247-254 [Conf]
  9. Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
    A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:3, pp:234-243 [Journal]
  10. Philippe Cauvet, Serge Bernard, Michel Renovell
    System-in-Package, a Combination of Challenges and Solutions. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:193-199 [Conf]
  11. Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
    "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:211-216 [Conf]
  12. Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
    "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:159-164 [Conf]
  13. V. Fresnaud, Lilian Bossuet, Dominique Dallet, Serge Bernard, J. M. Janik, B. Agnus, Philippe Cauvet, Ph. Gandy
    A Low Cost Alternative Method for Harmonics Estimation in a BIST Context. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:193-198 [Conf]
  14. Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell
    A-to-D converters static error detection from dynamic parameter measurement. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:10, pp:945-953 [Journal]
  15. Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell
    Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:291-298 [Journal]
  16. Vincent Kerzerho, Serge Bernard, Philippe Cauvet, J. M. Janik
    A First Step for an INL Spectral-Based BIST: The Memory Optimization. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:4-6, pp:351-357 [Journal]

  17. A Neural Stimulator Output Stage for Dodecapolar Electrodes. [Citation Graph (, )][DBLP]


  18. Considerations on Improving the Design of CUFF Electrode for ENG Recording - Geometrical Approach, Dedicated IC, Sensitivity, Noise Rejection. [Citation Graph (, )][DBLP]


  19. Multipolar Electrode and Preamplifier Design for ENG-Signal Acquisition. [Citation Graph (, )][DBLP]


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