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Pietro Babighian:
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- Pietro Babighian, Luca Benini, Enrico Macii
A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:500-505 [Conf]
- Pietro Babighian, Luca Benini, Enrico Macii
Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating. [Citation Graph (0, 0)][DBLP] DATE, 2004, pp:720-723 [Conf]
- Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii
Enabling fine-grain leakage management by voltage anchor insertion. [Citation Graph (0, 0)][DBLP] DATE, 2006, pp:868-873 [Conf]
- Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii
Low-overhead state-retaining elements for low-leakage MTCMOS design. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2005, pp:367-370 [Conf]
- Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii
Post-layout leakage power minimization based on distributed sleep transistor insertion. [Citation Graph (0, 0)][DBLP] ISLPED, 2004, pp:138-143 [Conf]
- Pietro Babighian, Luca Benini, Enrico Macii
A scalable algorithm for RTL insertion of gated clocks based on ODCs computation. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:29-42 [Journal]
- Pietro Babighian, Gila Kamhi, Moshe Y. Vardi
Interactive presentation: PowerQuest: trace driven data mining for power optimization. [Citation Graph (0, 0)][DBLP] DATE, 2007, pp:1078-1083 [Conf]
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